Highly reliable, 65 nm-node Cu dual damascene interconnects with full porous-SiOCH (k=2.5) films for low-power ASICs

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 60-61

  Ueki, M ^b   Narihiro, M ^b   Ohtake, H ^b   Tagami, M ^b   Tada, M ^b   Ito, F ^b   Harada, Y ^b   Abe, M ^b   Inoue, N ^b   Arai, K ^b   Takeuchi, T ^b   Saito, S ^b   Onodera, T ^b   Furutake, N ^b   Hiroi, M ^a   Sekine, M ^a   Hayashi, Y ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AGGLOMERATION; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COPPER; DIELECTRIC MATERIALS; ELECTRIC BREAKDOWN; ELECTROMIGRATION; ENERGY DISSIPATION; ETCHING; POROUS MATERIALS; RELIABILITY; THICK FILMS;

DIFFUSION BARRIERS; DUAL DAMASCENE INTERCONNECTS (DDI); PORE SEALING; TIME DEPENDENT DIELECTRIC BREAKDOWN (TDDB);

SEMICONDUCTING FILMS;

EID: 4544385389     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.2004.1345393     Document Type: Conference Paper

References (4)

1. Y. Hayashi, et.al., Proc. of IITC 2002, p145 (2002).
2. M. Tada, et.al., IEDM Tech. Digest, p845 (2003).
3. H. Ohtake, et.al., IEDM Tech. Digest, p853 (2003).
4. Y. Harada, et.al., Extend. Abst. of 2002 SSDM, p180 (2002).