Interconnecting device opportunities for gigascale integration (GSI)

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 525-528

  Meindl, James D ^a   Venkatesan, Raguraman ^a   Davis, Jeffrey A ^a   Joyner, James ^a   Naeemi, Azad ^a   Zarkesh Ha, Payman ^a   Bakir, Muhannad ^a   Mulé, Tony ^a   Kohl, Paul A ^a   Martin, Kevin P ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC CABLES; ELECTRIC CONDUCTIVITY; ELECTRIC INSULATORS; ELECTRIC LOSSES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; LSI CIRCUITS; PERFORMANCE; PERMITTIVITY; TRANSISTORS;

CLOCK FREQUENCY; GIGASCALE INTEGRATION; INPUT OUTPUT INTERCONNECT; INTERCONNECTING DEVICES; MICROPHOTONICS; REVERSE SCALING; RF WIRELESS INTERCONNECTS; SIGNAL INTEGRITY; SYSTEM ON A CHIP GLOBAL INTERCONNECT ARCHITECTURE;

INTERCONNECTION NETWORKS;

EID: 0035716692     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Scanning the issue
2. Low power microelectronics: Retrospect and prospect
3. International technology roadmap for semiconductors (ITRS)
4. A stochastic wire-length distribution for gigascale integration (GSI) - Part I: Derivation and validation
5. A stochastic wire-length distribution for gigascale integration (GSI) - Part II: Applications to clock frequency, power dissipation, and chip size estimation
6. Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
7. Interconnect limits on gigascale integration (GSI) in the 21st century
8. A three-dimensional stochastic wire length distribution for variable separation of strata
9. A global interconnect design window for a three-dimensional system-on-a-chip
10. Sea of leads: A disruptive paradigm for a system-on-a-chip (SoC)
11. Multi-I/O and reconfigurable RF/wireless interconnect based on near field capacitive coupling and multiple access techniques
12. Rationale and challenges for optical interconnects to electronic chips
13. Input coupling and guided-wave distribution schemes for board-level intra-chip guided-wave optical clock distribution network using volume grating coupler technology