Feasibility study of 45-nm-node scaled-down Cu interconnects with molecular-pore-stacking (MPS) SiOCH films

IEEE Transactions on Electron Devices

Volumn 54, Issue 4, 2007, Pages 797-806

  Tada, Munehiro ^a   Ohtake, Hiroto ^a   Ito, Fuminori ^a   Narihiro, Mitsuru ^a   Taiji, Toshiji ^b   Kasama, Yoshiko ^b   Takeuchi, Tsuneo ^a   Arai, Kouichi ^a   Furutake, N ^a   Oda, Noriaki ^b   Sekine, Makoto ^b   Hayashi, Yoshihiro ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

45 nm node; Cu; Damascene; Interconnects; Porous dielectric (porous low k); Reliability

Indexed keywords

CAPACITANCE; COPPER; ELECTRIC CONDUCTIVITY; ELECTRON SCATTERING; PERMITTIVITY; SEMICONDUCTING FILMS;

DIELECTRIC RELIABILITY; LINE-ASPECT CONTROL; MOLECULAR-PORE-STACKING;

LARGE SCALE SYSTEMS;

EID: 34147141270     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.892357     Document Type: Article

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