A robust embedded Ladder-oxide/Cu multilevel interconnect technology for 0.13 μm CMOS generation

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2002, Pages 34-35

  Oda, N ^a   Ito, S ^a   Takewaki, T ^a   Kunishima, H ^a   Hironaga, N ^a   Honma, I ^a   Namba, H ^a   Yokogawa, S ^a   Goto, T ^a   Usami, T ^a   Ohto, K ^a   Kubo, A ^a   Aoki, H ^a   Suzuki, M ^a   Yamamoto, Y ^a   Watanabe, S ^a   Takeda, T ^a   Yamada, K ^a   Koska, M ^a   Horiuchi, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COPPER; ELECTRIC WIRING; ELECTROMIGRATION; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS; METALLIZING; VLSI CIRCUITS;

DAMASCENCE;

CMOS INTEGRATED CIRCUITS;

EID: 0036045989     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)