A new direct low-k/Cu dual damascene (DD) contact lines for low-loss (LL) CMOS device platforms

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2008, Pages 106-107

  Kawahara, J ^a   Ueki, M ^a   Tagami, M ^a   Yako, K ^a   Yamamoto, H ^a   Ito, F ^a   Nagase, H ^a   Saito, S ^a   Furutake, N ^a   Onodera, T ^a   Takeuchi, T ^a   Nakamura, H ^b   Arita, K ^b   Motoyama, K ^b   Nakazawa, E ^b   Fujii, K ^b   Sekine, M ^b   Okada, N ^b   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

CMOS; Cu contact; Low parasitic elements; Low k

Indexed keywords

CMOS; CMOS DEVICES; CONTACT LINES; CONTACT-RESISTANCE; CU CONTACT; DUAL DAMASCENE; LOW LOSSES; LOW PARASITIC ELEMENTS; LOW-K; LOW-PARASITIC; LOW-RESISTANCE; METAL-DIELECTRICS; ON CURRENTS; RELIABILITY DEGRADATION; VLSI TECHNOLOGIES;

COST EFFECTIVENESS; METALS; SULFATE MINERALS; TECHNOLOGY;

ASPECT RATIO;

EID: 51949102877     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2008.4588580     Document Type: Conference Paper

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