Materials' impact on interconnect process technology and reliability

IEEE Transactions on Semiconductor Manufacturing

Volumn 18, Issue 1, 2005, Pages 69-85

  Hussein, Makarem A ^a   He, Jun ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Copper; Dual damascene; Interconnects; Low k; Reliability

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; DIELECTRIC MATERIALS; DIFFUSION; ELECTRIC CONDUCTANCE; ELECTRIC RESISTANCE; METALLIZING; PERMITTIVITY; RELIABILITY;

DUAL DAMASCENE; INTERCONNECTS; INTERLAYER DIELECTRIC (ILD) MATERIALS; LOW K;

INTERCONNECTION NETWORKS;

EID: 13844296467     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.841832     Document Type: Article

References (65)

1. S. P. Jeng, R. H. Havemann, and M. C. Chang, "Process integration and manufacturability issues for high performance multilevel interconnect," in Proc. Advanced Metallization for Devices and Circuits-Science, Technology, and Manufacturability Symp. Pittsburgh, PA, 1994, pp. 25-31.
2. M. Bohr, "Interconnect scaling - The real limiter to high performance ULSI," in Tech. Dig. Int. Electron Devices Meeting. Piscataway, NJ, Dec. 10-13, 1995, pp. 241-244.
3. _, "Silicon trends and limits for advanced microprocessors," in Commun. ACM, vol. 41, Mar. 1998, pp. 80-87.
4. S. P. Murarka and S. W. Hymes, "Copper metallization for ULSI and beyond," Critical Rev. Solid State Mater. Sci., vol. 20, no. 2, pp. 87-124, 1995.
5. T. Licata, E. G. Colgan, J. M. Harper, and S. E. Luce, "Interconnect fabrication processes and the development of low-cost wiring for MOS products," IBM J. Res. Develop., vol. 39, no. 4, pp. 419-435, Jul. 1995.
6. The International Technology Roadmap for Semiconductors (ITRS) (2000). [Online]. Available: www.sematech.org
7. A. Kajita, T. Usui, M. Yamada, E. Ogawa, T. Katata, A. Sakata, H. Miyajima, A. Kojima, R. Kanamura, Y. Ohoka, H. Kawashima, K. Tabuchi, K. Nagahata, Y. Kato, T. Hayashi, S. Kadomura, and H. Shibata, "Highly reliable Cu/low-k dual damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM," in Proc. Int. Interconnect Technol. Conf. Piscataway, NJ, Jun. 2-4, 2003, pp. 9-11.
8. M. Assous, J. Simon, L. Broussous, C. Bourlot, M. Fayolle, O. Louveau, A. Roman, E. Tabouret, H. Feldis, D. Louis, and J. Torres, "Porous dielectric dual damascene patterning issues for 65 nm node: Can architecture bring a solution?," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2003, pp. 97-99.
9. T. Furusawa, S. Machida, D. Ryuzki, K. Sameshima, T. Ishida, K. Ishikawa, N. Miura, N. Konishi, T. Saito, and H. Yamaguchi, "Novel dissoluble hardmask for damage-less Cu/Low-k interconnect fabrication," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2003, pp. 195-197.
10. Y. Furukawa, R. Wolters, and M. Patz, "Linewidth-narrowing due to 193 nm resist deformation during etch of spin-on low-k dielectrics," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2003, pp. 150-152.
11. Y. K. Siew, R. Joy, D. Tan, W. Liu, R. Srivastawa, J. B. Tan, and L. Hsia, "Trench etch optimization with 193 nm resist," Semiconductor Int., pp. 62-66, Aug. 2003.
12. R. F. Schnabel, D. Dobuzinsky, J. Gambino, K. P. Muller, F. Wang, D. C. Perng, and H. Palm, "Dry etch challenges of 0.25 μm dual damascene structures," Microelectronic Eng., vol. 37/38, pp. 59-65, 1997.
13. S. Lin, C. Chen, S. Huang, T. Kang, C. Yeh, T. Li, B. Tsui, and C. Hsia, "An optimized integration scheme for 0.13 μm technology node dual damascene Cu interconnect," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2000, pp. 273-275.
14. G. Y. Lee, Z. G. Lu, D. M. Dobuzinsky, X. J. Nin, and G. Costrini, "Dielectric anti-reflection coating application in a 0.175 μm dual-damascene process," in Proc. IEEE Int. Interconnect Technology Conf., Jun. 1-3, 1998, pp. 87-89.
15. S. Deshpande, S. Xie, J. Lamb III, and N. Brakensiek, "Advancements in organic anti-reflective coatings for dual damascene processes," in Proc. SPIE - Int. Soc. Opt. Eng., vol. 3998, 2000, pp. 797-805.
16. M. Hussein and S. Sivakumar, "A novel approach to dual damascene patterning," in Proc. IEEE Int. Interconnect Technology Conf., Jun. 2-4, 2002, pp. 18-20.
17. eff < 3.0) dielectrics using FLARE™ and an organo-silicate hard mask," in Tech. Dig. Int. Electron Devices Meeting, Dec. 5-8, 1999, pp. 623-626.
18. P. A. Kohl, D. M. Bhusari, M. Wedlake, C. Case, F. P. Klemens, J. Miner, L. Byung-Chan, R. J. Gutmann, and R. Shick, "Air-gaps in 0.3 μm electrical interconnections," Electron Device Lett., vol. 21, no. 12, pp. 557-559, Dec. 2000.
19. J. J. Waeterloos, E. O. Shaffer II, T. Stokich Jr., J. Hetzner, D. Price, L. Booms, R. A. Donaton, G. Beyer, B. Coenegrachts, R. Caluwaerts, H. Struyf, Z. S. Tokei, I. Vervoort, B. Sijmus, I. Vos, K. Maex, T. Komiya, and M. Iwashita, "Integration of a low permittivity spin-on embedded hardmask for Cu/SiLK resin dual damascene," in Proc. IEEE Int. Interconnect Technol. Conf., Jun. 4-6, 2001, pp. 60-62.
20. M. Hussein, R. Brain, R. Turkot, J. Leu, V. Singh, and S. Sivakumar, "Dual damascene patterning of polymer interlayer dielectrics," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2003, pp. 33-35.
21. K. Tokashiki, T. Maruyama, and A. Nishizawa, "Influence of process chamber ambient on SiOC (k = 2.9) ILD Cu damascene ashing," IEEE Trans. Semiconduct. Manufact., vol. 17, no. 3, pp. 305-310, Aug. 2004.
22. K. Higashi, N. Nakamura, H. Miyajima, S. Satoh, A. Kojima, J. Abe, K. Nagahata, T. Tatsumi, K. Tabuchi, T. Hasegawa, H. Kawashima, S. Arakawa, N. Matsunaga, and H. Shibata, "A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM," in Proc. IEEE Int. Interconnect Technology Conf., Jun. 3-5, 2002, pp. 15-17.
23. A. Matsushita, N. Ohashi, K. Inukai, H. J. Shin, S. Sone, K. Sudou, K. Misawa, I. Matsumoto, and N. Kobayashi, "Low damage ashing using H2/He plasma for porous ultra low-k," in Proc. IEEE Int. Interconnect Technology Conf., Jun. 2-4, 2003, pp. 147-149.
24. Handbook of Thin Film Materials, vol. 1, H. S. Nalwa, Ed., 2002, p. 103.
25. S. M. Rossnagel, A. Sherman, and F. Turner, "Plasma-enhanced atomic layer deposition of Ta and Ti for interconnect diffusion barriers," J. Vacuum Sci. Technol. B (Microelectronics Nanometer Structures), vol. 18, no. 4, pp. 2016-2020, Jul. 2000.
26. The International Technology Roadmap for Semiconductors (ITRS) (2003). [Online]. Available: www.sematech.org
27. Y. Yamada, N. Konishi, N. Ohashi, and T. Kimura, "Improved Cu abrasive-free polishing at 0.13 mm manufacturing and beyond," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2002, pp. 108-110.
28. S. Lakshminarayanan, P. Wright, and J. Pallinti, "Design rule methodology to improve the manufacturability of copper CMP process," in Proc. Int. Interconnect Technology Conf. Piscataway, NJ, Jun. 2-4, 2002, pp. 99-101.
29. G. Raghavan, C. Chiang, P. B. Anders, S. Tzeng, R. Villasol, P. Bai, M. Bohr, and D. B. Fraser, "Diffusion of copper through dielectric films under bias temperature stress," Thin Solid Films, vol. 262, pp. 168-176, 1995.
30. I. A. Blech, "Electromigration in thin aluminum films on titanium nitride," J. Appl. Phys., vol. 47, pp. 1203-1208, 1976.
31. S. Rhee, Y. Du, and P. S. Ho, "Thermal stress characteristics of Cu/oxide and Cu/low-k submicron interconnect structures," J. Appl. Phys., vol. 93, pp. 3926-33, 2003.
32. R. S. Sprbello, "Microscopic driving forces for electronmigration, " in Proc. Mater. Research Soc. Symp., vol. 427, 1996, pp. 73-81.
33. J. R. Lloyd, "Electromigration in integrated circuit conductors," J. Phys. D (Appl. Phys.), vol. 32, pp. R109-R118, 1999.
34. C.-K. Hu, L. Gignac, and R. Rosenberg, "Reduced electromigration of Cu wires by surface coating," Appl. Phys. Lett., vol. 81, pp. 1782-1784, 2002.
35. W. M. Lane, E. Liniger, and J. R. Lloyd, "Relationship between interfacial adhesion and electromigration in Cu metallization," J. Appl. Phys., vol. 93, pp. 1417-1421, 2003.
36. R. G. Filippi, R. A. Wachnik, H. Aochi, J. R. Lloyd, and M. A. Korhonen, "The effect of current density and stripe length on resistance saturation during electromigration testing," Appl. Phys. Lett., vol. 69, pp. 2350-2352, 1996.
37. S. P. Hau-Riege, "Probabilistic immortality of Cu damascene interconnects," J. Appl. Phys., vol. 91, pp. 2014-2022, 2002.
38. Z. Suo, "Reliability of interconnect structures," in Interfacial and Nanoscale Failure, W. Gerberich and W. Yang, Eds., 2003, pp. 265-324.
39. C. S. Hau-Riege and C. V. Thompson, "The effects of microstructural transitions at width transitions on interconnect reliability," J. Appl. Phys., vol. 87, pp. 8467-8472, 2000.
40. C. S. Hau-Riege, A. P. Marathe, and V. Pham, "The effect of low-k ILD on the electromigration reliability of Cu interconnects with different line lengths," in Proc. 41st Annu. IEEE Int. Reliability Physics Symp. Dallas, TX, 2003, pp. 173-177.
41. J. He, Z. Suo, T. N. Marieb, and J. A. Maiz, "Electromigration lifetime and critical void volume," Appl. Phys. Lett., vol. 85, pp. 4639-4641, 2004.
42. P.-C. Wang and R. G. Filippi, "Electromigration threshold in copper interconnects," Appl. Phys. Lett., vol. 78, pp. 3598-3600, 2001.
43. Y. Zhou, T. Scherban, G. Xu, J. He, B. Miner, C.-H. Jan, A. Ott, J. O'Loughlin, D. Ingerly, and J. Leu, "Impact of interfacial chemistry on adhesion and electromigration in Cu interconnects," in Proc. Advance Metallization Conf., San Diego, CA. to be published.
44. J. Curry, G. Fitzgibbon, Y. Guan, R. Muollo, G. Nelson, and A. Thomas, "New failure mechanisms in sputtered aluminum-silicon films," in Proc. IEEE Int. Reliability Phys. Symp., 1984, pp. 6-8.
45. E. T. Ogawa, J. W. McPherson, J. A. Rosal, K. J. Dickerson, T.-C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifield, J. C. Ondrusek, and W. R. McKee, "Stress-induced voiding under vias connected to wide Cu metal leads," in Proc. IEEE Int. Reliability Phys. Symp., 2002, pp. 312-321.
46. K. Y. Y. Doong, R. C. J. Wang, S. C. Lin, and L. J. Hung, "Stress-induced voiding and its geometry dependency characterization," in Proc. IEEE Int. Reliability Phys. Symp., 2003, pp. 156-160.
47. K. Yoshida, T. Fujimaki, K. Miyamoto, and T. Honma, "Stress-induced voiding phenomena for an actual CMOS LSI interconnects," in Proc. IEEE Int. Electron Device Meeting, 2002, pp. 753-756.
48. T. C. Huang, C. H. Yan, W. K. Wan, C. C. Hsia, and M. S. Liang, "Numerical modeling and characterization of the stress migration behavior upon various 90 nanometer Cu/low k interconnects," in Proc. IEEE Int. Interconnect Technology Conf., 2003, pp. 207-209.
49. J. W. McPherson and C. F. Dunn, "A model for stress-induced notching and voiding in very large-scale integrated Al-Si (1%) metallization," J. Vac. Sci. Techol., pp. 1321-1325, 1987.
50. T. Harada, K. Kobayashi, M. Takashi, K. Nii, A. Ikeda, T. Ueda, and T. Yabu, "Reliability improvement of Cu interconnects by additional anneal between Cu CMP and barrer cap," in Proc. IEEE Int. Interconnect Technology Conf., 2003, pp. 92-94.
51. G. Xu, J. He, E. Andideh, J. Bielefeld, and T. Scherban, "Cohesive strength characterization of brittle low-k films," in Proc. IEEE Int. Interconnect Technology Conf., 2002, pp. 57-59.
52. T. Scherban, B. Sun, J. Blaine, C. Block, B. Jin, and E. Andideh, "Interfacial adhesion of copper-low k interconnects," in Proc. IEEE Int. Interconnect Technology Conf., 2001, pp. 257-259.
53. G. G. Harman and C. E. Johnson, "Wire bonding to advanced copper, low-k integrated circuits, the metal/dielectric stacks, and materials considerations," IEEE Trans. Comput. Packag. Technol., vol. 25, pp. 677-683, 2002.
54. M. R. Miller and P. S. Ho, "Interfacial adhesion study for Cu/SiLK interconnects in flip-chip packages," in Proc. 51st Electron. Comp. Technol. Conf., 2001, pp. 965-970.
55. J. W. Hutchinson and Z. Suo, "Mixed mode cracking in layered materials," in Advances in Applied Mechanics. New York: Academic, 1991, vol. 29.
56. Q. Ma, J. Xie, S. Chao, S. El-Mansy, R. McFadden, and H. Fujimoto, "Channel cracking technique for toughness measurement of brittle dielectric thin films on silicon substrates," in Proc. Mater. Res. Soc. Symp., vol. 516, 1998, pp. 331-336.
57. G. Wang, S. Groothuis, and P. S. Ho, "Effect of packaging on interfacial cracking in Cu/low k damascene structures," in Proc. 53rd Electron. Comp. Technol. Conf., 2003, pp. 727-732.
58. L. L. Mercado, S.-M. Kuo, C. Goldberg, and D. Frear, "Impact of flip-chip packaging on copper/low-k structures," IEEE Trans. Adv. Packag., vol. 26, pp. 433-440, 2003.
59. M. Rasco, K. Mosig, J. Ling, and P. Elenius, "Packaging assessment of porous ultra low-k materials," in Proc. IEEE Int. Interconnect Technology Conf., 2002, pp. 113-115.
60. E. Beyne, "Cu interconnects and low-k dielectric, challenges for chip interconnections and packaging," in Proc. IEEE Int. Interconnect Technology Conf., 2003, pp. 221-223.
61. J. Li, Q. Ye, A. Cassell, J. Koehne, H. T. Ng, J. Han, and M. Meyyappan, "Carbon nanotube interconnects: A process solution," in Proc. IEEE Int. Interconnect Technology Conf., 2003, pp. 271-272.
62. E. G. Liniger, C.-K. Hu, and L. M. Gignac, "Effect of liner thickness on electromigration lifetime," J. Appl. Phys., vol. 93, pp. 9576-9582, 2003.
63. M. Saran et al., "Elimination of bond-pad damage through structural reinforcement of intermetal dielectrics," in Proc. IEEE Int. Reliability Phys. Symp., 1998, pp. 225-231.
64. R. Emery, S. Towle, H. Braunisch, and C. Hu, "Novel microelectronic packaging method for reduced thermomechanical stresses on low dielectric constant materials," in Proc. Adv. Metallization Conf., 2001, pp. 143-149.
65. Q. Zhu, L. Ma, and S. K. Sitaraman, "Design optimization of one-turn helix: A novel compliant off-chip interconnect," IEEE Trans. Adv. Packag., vol. 26, pp. 106-112, 2003.