45nm-node interconnects with porous SiOCH-stacks, tolerant of low-cost packaging applications

Proceedings of the IEEE 2007 International Interconnect Technology Conference - Digest of Technical Papers

Volumn , Issue , 2007, Pages 181-183

  Inoue, N ^a   Tagami, M ^a   Itoh, F ^a   Yamamoto, H ^a   Takeuchi, T ^a   Saito, S ^a   Furutake, N ^a   Ueki, M ^a   Tada, M ^a   Suzuki, T ^b   Hayashi, Y ^a  

^a NEC CORPORATION   (Japan)

^b Sumitomo Bakelite Co Ltd   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL BONDS; CHIP SCALE PACKAGES; FAILURE ANALYSIS; POROUS MATERIALS; RELIABILITY THEORY; SEMICONDUCTING SILICON COMPOUNDS;

FINE-PITCHED BONDING-PAD; LOW-K STACK STRUCTURES; PBGA PACKAGE; WIRE-BOND RELIABILITY;

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 34748870316     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iitc.2007.382384     Document Type: Conference Paper

References (6)

1. M. Tagami, et.al., IITC 2005, p.12 (2005)
2. C. J. Uchibori, et.al., IITC 2006, p.196 (2006)
3. T. C. Huang, et. al., IITC 2006, p.92 (2006)
4. M. Tagami, et.al., VLSI Tech. Symp. p.134 (2006)
5. F. Ito, et.al., Proc. of ADMETA, p10 (2005).
6. Y. Hayashi, et al., IITC, p225 (2004).