A stochastic wire-length distribution for gigascale integration (gsi)-part II: Applications to clock frequency, power dissipation, and chip size estimation

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 590-597

  Davis, Jeffrey A ^a   De Vivek, K ^a   Meindlmicroelectronics, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Average wire length; Critical path; Die area estimation; Power dissipation model; Rent's rule; Wire length distribution

Indexed keywords

ELECTRIC LOSSES; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS;

DIE AREA ESTIMATION; GIGASCALE INTEGRATION (GSI); RENT'S RULE; WIRE LENGTH DISTRIBUTION;

VLSI CIRCUITS;

EID: 0032025521     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661220     Document Type: Article

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