Interconnect design strategy: structures, repeaters and materials with strategic system performance analysis (s2pal) model

IEEE Transactions on Electron Devices

Volumn 48, Issue 2, 2001, Pages 239-251

  Takahashi, Shuji ^a   Edahiro, Masato ^a   Hayashi, Yoshihiro ^b  

^a System LSI Design Engineering Division   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

Delay modeling; Interconnect structure; Repeater insertion; Signal delay

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRONICS PACKAGING; INTERCONNECTION NETWORKS;

INTERCONNECT DESIGN STRATEGY;

LSI CIRCUITS;

EID: 0035250092     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.902722     Document Type: Article

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