Integration of high-k gate stack systems into planar CMOS process flows

Extended Abstracts of International Workshop on Gate Insulator, IWGI 2001

Volumn , Issue , 2001, Pages 2-11

  Huff, H R ^a   Agarwal, A ^a   Kim, Y ^a   Perrymore, L ^a   Riley, D ^a   Barnett, J ^a   Sparks, C ^a   Freiler, M ^a   Gebara, G ^a   Bowers, B ^a   Chen, P J ^a   Lysaght, P ^a   Nguyen, B ^a   Lim, J E ^a   Lim, S ^a   Bersuker, G ^a   Zeitzoff, P ^a   Brown, G A ^a   Young, C ^a   Foran, B ^a   Shaapur, F ^a   Hou, A ^a   Lim, C ^a   Alshareef, H ^a   Borthakur, S ^a   Derro, D J ^a   Bergmann, R ^a   Larson, L A ^a   Gardner, M I ^a   Gutt, J ^a   Murto, R W ^a   Torres, K ^a   Jackson, M D ^a   more..

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LOGIC GATES; RECONFIGURABLE HARDWARE;

CMOS PROCESSS; CMOS TRANSISTORS; FABRICATION PROCESS; GATE STACKS; HIGH-K GATE STACKS; OXYGEN PARTIAL PRESSURE;

GATE DIELECTRICS;

EID: 84954160798     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWGI.2001.967538     Document Type: Conference Paper

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