MOS capacitance measurements for high-leakage thin dielectrics

IEEE Transactions on Electron Devices

Volumn 46, Issue 7, 1999, Pages 1500-1501

  Yang, Kevin J ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

SHUNT PARASITIC RESISTANCES;

CAPACITANCE MEASUREMENT; DIELECTRIC MATERIALS; ELECTRIC IMPEDANCE MEASUREMENT; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; SEMICONDUCTOR DEVICE MODELS; VOLTAGE MEASUREMENT;

MOS CAPACITORS;

EID: 0032679052     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.772500     Document Type: Article

References (6)

1. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantum mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's," IEEE Electron Device Lett., vol. 18, pp. 209-211, May 1997.
2. S.-W. Lee, "A capacitance-based method for experimental determination of metallurgical channel length in submicron LDD MOSFET's," IEEE Trans. Electron Devices, vol. 41, pp. 403-412, Mar. 1994.
3. C.-L. Huang, J. V. Faricelli, and N. D. Arora, "A new technique for measuring MOSFET inversion layer mobility," IEEE Trans. Electron Devices, vol. 40, pp. 1134-1139, June 1993.
4. A. Koukab, A. Bath, and E. Losson, "An improved high-frequency C - V method for interface state analysis on MIS structures," Solid-State Electron., vol. 41, no. 4, pp. 634-641, 1997.
5. Semiconductor Industry Assoc., The National Technology Roadmap for Semiconductors: Technology Needs, 1997.
6. J. F. Lønnum and J. S. Johannessen, "Dual-frequency modified C/V technique," Electron. Lett., vol. 22, no. 9, pp. 456-457, Apr. 1986.