Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 174-175

  Ghani, T ^a   Mistry, K ^a   Packan, P ^a   Thompson, S ^a   Stettler, M ^a   Tyagi, S ^a   Bohr, M ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS;

SHORT CHANNEL EFFECTS (SCE); SOURCE-DRAIN EXTENSION (SDE);

CMOS INTEGRATED CIRCUITS;

EID: 0033697180     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)