Challenges in integrating the high-k gate dielectric film to the conventional CMOS process flow

Materials Research Society Symposium - Proceedings

Volumn 670, Issue , 2001, Pages K211-K2111

  Agarwal, Avinash ^a   Freiler, Michael ^a   Lysaght, Pat ^a   Perrymore, Loyd ^a   Bergmann, Renate ^a   Sparks, Chris ^a   Bowers, Bill ^a   Barnett, Joel ^a   Riley, Deborah ^a   Kim, Yudong ^a   Nguyen, Billy ^a   Bersuker, Gennadi ^a   Shero, Eric ^a   Lim, Jae E ^a   Lin, Steven ^a   Chen, Jerry ^a   Murto, Robert W ^a   Huff, Howard R ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; ELECTRODES; GATES (TRANSISTOR); HIGH TEMPERATURE EFFECTS; INTERFACES (MATERIALS); MOSFET DEVICES; PLASMA ETCHING; THERMODYNAMIC STABILITY;

GATE DIELECTRIC FILMS;

DIELECTRIC FILMS;

EID: 17144474099     PISSN: 02729172     EISSN: None     Source Type: Journal    
DOI: 10.1557/proc-670-k2.1     Document Type: Article

References (22)