Arbitrary modeling of TSVs for 3D integrated circuits

Arbitrary Modeling of TSVs for 3D Integrated Circuits

Volumn , Issue , 2015, Pages 1-179

  Salah, Khaled ^a   Ismail, Yehea ^b   El Rouby, Alaa ^a  

^a MENTOR GRAPHICS CORPORATION   (United States)

^b AMERICAN UNIVERSITY IN CAIRO   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS; SPICE; TIMING CIRCUITS;

ARBITRARY MODELS; BAND PASS FILTERING; CLOSED-FORM EQUATIONS; DIMENSIONAL ANALYSIS; SPICE-COMPATIBLE; TECHNOLOGY INDEPENDENT; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84944198657     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-3-319-07611-9     Document Type: Book

References (196)

1. The International Technology Roadmap for Semiconductors (ITRS), 2012 [Online]. http://www.itrs.net. Accessed 2013
2. K. Roy, B. Jung, A. Raghunathan, Integrated systems in the More-than-Moore era: designing low-cost energy-efficient systems using heterogeneous components, in 23rd International Conference on VLSI Design, 2010
3. Z. Lu, A. Jantsch, Trends of terascale computing chips in the next ten years, ASICON, 2009
4. A.M. Ionescu, Nanoelectronics roadmap: evading Moore's law, EWME, 2009
5. D. Rairigh, Limits of CMOS technology scaling and technologies Beyond-CMOS, IEEE, 2005
6. M.C. Wang, Independent-gate FinFET circuit design methodology. IAENG Int. J. Comp. Sci. 37, 1 (2010)
7. R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, L.-R. Zheng, Compact modelling of through-silicon vias (TSVs) in three dimensional (3-D) integrated circuit, in Proceeding of IEEE International Conference on 3D System Integration (3D IC), San Francisco, USA, 2009
8. L.P. Carloni, Y. Xie, Networks-on-chip in emerging interconnect paradigms: advantages and challenges, IEEE, 2009
9. D. Goswami, Optical computing. Resonance 8(6), 56-71 (2003)
10. K. Bergman, L.P. Carloni, J.A. Kash, Y. Vlasov, On-chip photonic communication for highperformance multi-core processors, IEEE, 2009
11. A. Gupta, B.C. Kim, S. Kannan, S.S. Evana, L. Li, Analysis of CNT based 3D TSV for emerging RF applications, in Electronic Components and Technology Conference, 2011
12. B. Kim, S. Kannan, A. Gupta, S. Noh, L. Li, Characterization of high performance CNTbased TSV for radar applications, in IEEE 13th Electronics Packaging Technology Conference, 2011
13. S. Kannan, B. Kim, A. Gupta, S. Noh, L. Li, Characterization of high performance CNTbased TSV for high-frequency RF applications. Adv. Mater. Res. 1(1), 37-49 (2012)
14. http://www.physorg.com/news90607516.html. Accessed 2013
15. S. Hassan, M. Asghar, Limitation of silicon based computation and future prospects, in Second International Conference on Communication Software and Networks, 2010
16. J.F. Podevin, T. Munakata, Beyond silicon new computing paradigms. Commun. ACM 50(9), 30-34 (2007)
17. S. Khullar, V. Chopra, M.S. Kahlon, DNA computing: migrating from silicon chip to test tubes, in Proceeding of National Conference on Challenges & Opportunity in Information Technology, COIT 2007, March 23 (RIMT-IET, Mandi Gobindgarh, 2007), pp. 72-75
18. L.M. Adleman, Computing with DNA. Sci. Am. 279(2), 54-61 (1998)
19. Z. Ramjan, Quantum computing, CS 664 (Spring 2005), http://zack.ramjanfamily.com/cs664/Quantum_Paper.pdf. Accessed Oct 2009
20. K. Siozios, A. Bartzas, D. Soudris, Architecture-level exploration of alternative interconnection schemes targeting 3D FPGAs: a software-supported methodology. Int. J. Reconfig. Comput. 2008, 8 (2008)
21. D.H. Kim, S. Mukhopadhyay, S.K. Lim, TSV aware interconnect length and power prediction for 3D stacked ICs, in IEEE International Interconnect Technology Conference (2009), pp. 26-28
22. K. Banerjee, S.J. Souri, P. Kapur, K.C. Saraswat, 3-d ics: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89(5), 602-633 (2001)
23. K.P. Stuby, Hourglass-shaped conductive connection through semiconductor structures. U.S. Patent 3648131, Assignee: IBM, Filing Date: 7 Nov 1969, Issue Date: 7 March 1972
24. J.F. Li, C.W. Wu, Is 3D integration an opportunity or just a hype? in ASPDAC, 2010
25. L.P. Carloni, P. Pande, Y. Xie, Networks-on-chip in emerging interconnect paradigms: advantages and challenges, in NOCs, 2009
26. Y. Xie, J. Cong, S. Sapatnekar, Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures (Springer, Boston, 2010)
27. V.F. Pavlidis, E.G. Friedman, Three-Dimensional Integrated Circuit Design (Elsevier, 2011)
28. A. Papanikolaou, D. Soudris, R. Radojcic, Three Dimensional System Integration (Springer, New York, 2011)
29. C. Ryu, J. Kim, Electrical characterization of through silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation, in Electromagnetic Electronic Materials and Packaging, 2007 Conference (May 2008), pp. 351-354
30. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, J. Kim, High frequency electrical model of through wafer via for 3-D stacked chip packaging, in Electronics System integration Technology Conf, vol. 1 (Sept 2006), pp. 215-220
31. D.M. Jang, C. Ryu, K.Y. Lee, B.H. Cho, J. Kim, T.S. Oh, W.J. Lee, J. Yu, Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV), in Proc. of ECTC (2007), pp. 847-852
32. C. Ryu, J. Kim, J.S. Pak, Multi-stacked through-silicon-via effects on signal integrity and power integrity for application of 3-dimensional stacked-chip-package, in IEEE, 2009
33. S.W. Ho, S.W. Yoon, Q. Zhou, K. Pasad, V. Kripesh, J.H. Lau, High RF performance TSV silicon carrier for high frequency application, in Electronic Components and Technology Conference, 2008
34. A. Beece, K. Rose, T. Zhang, J. Qiang, Modeling and evaluation for electrical characteristics of through-strata-vias (TSVs) in three-dimensional integration, in IEEE International Conference in 3D System Integration, 2009, 3DIC 2009
35. J. Shim, E. Song, J. Pak, J. Lee, H. Lee, K. Park, J. Kim, Active circuit to through silicon via (TSV) noise coupling, in Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09, IEEE 18th Conference
36. J. Kim, E. Song, J. Cho, J. Pak, J. Lee, H. Lee, K. Park, J. Kim, Through silicon via (TSV) equalizer, in Electrical Performance of Electronic Packaging and Systems, 2009. EPEPS '09, IEEE 18th Conference
37. M. Rousseau, O. Rozeau, G. Cibrario, G.L. Carval, M.A. Jaud, P. Leduc, A. Farcy, A. Marty, Through-silicon via based 3D IC technology: electrostatic simulations for design methodology, in IMAPS Device Packaging Conference, Phoenix, AZ, USA, 2008
38. I. Savidis, E.G. Friedman, Electrical modeling and characterization of 3-D vias, in Proceedings of IEEE International Symposium on Circuits and Systems, May 2008
39. I. Savidis, E.G. Friedman, Closed-form expressions of 3-D via resistance, inductance, and capacitance. IEEE Transac. Electr. Dev. 56(9), 1873-1881 (2009)
40. R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, L.-R. Zheng, Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits (ICs), in Proceedings of Workshop 3-D Integration, DATE Conference, April 2009
41. E. Eid, T. Lacrevaz, S. de Rivaz, C. Bermond, B. Flchet, F. Calmon, C. Gontrand, A. Farcy, L. Cadix, P. Ancey, Predictive high frequency effects of substrate coupling in 3D integrated circuits stacking, in 3D System Integration, 2009, 3DIC 2009
42. L. Cadix, A. Farcy, C. Bermond, C. Fuchs, P. Leduc, Modelling of through silicon via RF performance and impact on signal transmission in 3D integrated circuits, in IEEE International Conference in 3D System Integration, 2009, 3DIC 2009
43. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, R. Tummala, Electrical modeling of through silicon and package vias, in IEEE International Conference in 3D System Integration, 2009. 3DIC 2009
44. C. Xu, H. Li, R. Suaya, Compact AC modeling and analysis of Cu, W, and CNT based through-silicon vias (TSVs) in 3-D ICs, in IEDM09-521, 2009
45. M. Stucchi, K.D. Meyer, W. Dehaene, S.G. Katti, Electrical modeling and characterization of through silicon via for three-dimensional ICs. IEEE Transac. Electr. Dev. 57(1) (2010)
46. D.E. Khali, Y.I. Ismail, M. Khellah, T. Karnik, V. De, Analytical model for the propagation delay of through silicon vias, in Proceedings of IEEE International Symposium of Quality Electronic Design (March 2008), pp. 553-556
47. I. Savidis, S. Alam, A. Jain, S. Pozder, R. Jones, R. Chatterjee, Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits. Microelectr. J. 41(1), 9-16 (2010)
48. R. Weerasekera, D. Pamunuwa, M. Grange, H. Tenhunen, L.-R. Zheng, Closed-form equations for through-silicon via (TSV) parasitics in 3-D integrated circuits, in Proceedings of Workshop 3-D Integration, DATE Conference, April 2009
49. P. Leduca, F.d. Crécya, M. Fayollea, B. Charleta, T. Enota, M. Zussya, B. Jonesb, J.C. Barbea, N. Kerneveza, S. Maitrejeana, D. Louisa, G. Passemardc, Challenges for 3D IC integration: bonding quality and thermal managementc, IEEE, 2007
50. T.Y. Chiang, S.J. Souri, C.O. Choi, K.C. Saraswat, Thermal analysis of heterogeneous 3-D ICs with various integration schemes, in Proceedings of IEEE Electron Devices Meeting (2001), pp. 681-684
51. C. Chiang, S. Sinha, The road to 3D EDA tool readiness, in Proceedings of 2009 Conference on Asia and South Pacific Design Automation (2009), pp. 429-436
52. A. Rahman, R. Reif, System-level performance evaluation of three-dimensional integrated circuits. IEEE Trans. VLSI Syst. (Special Issue on System-Level Interconnect Prediction) 8(6), 671-678 (2000)
53. Synopsys Design Compiler, http://www.synopsis.com/
54. Cadence Silicon Ensemble, http://www.cadence.com/
55. MIT PR3D, http://mtlweb.mit.edu/researchgroups/icsystems/3dcsg/downloads.html
56. B. Vaidyanathan, W.-L. Hung, F. Wang, Y. Xie, V. Narayanan, M.J. Irwin, Architecting microprocessor components in 3D design space, www.cse.psu.edu/~yuanxie/Papers/VLSID07- 3D.pdf
57. Synopsis PrimeTime, http://www.synopsis.com/
58. T. Yan, Q. Dong, Y. Takashima, Y. Kajitani, How does partitioning matter for 3D floorplanning? in Proceedings of GLSVLSI (April 2006), pp. 73-78
59. M. Pathak, Y. Joon Lee, T. Moon, S.K. Lim, Through silicon via management during 3D physical design: when to add and how many? in IEEE International Conference on Computer- Aided Design (ICCAD), 2010
60. W. Hung, G. Link, Y. Xie, N. Vijaykrishnan, M.J. Irwin, Interconnect and thermal-aware floorplanning for 3D microprocessors, in Proceedings of ISQED (March 2006), pp. 98-104
61. Y.J. Lee, S.K. Lim, Routing optimization of multi-modal interconnects in 3D ICs, in Proceedings of the 2009 Electronic Components and Technology Conference (May 2009), pp. 32-39
62. K. Bernstein, P. Andry, J. Cann, P. Emma, D. Greenberg, W. Haensch, M. Ignatowski, S. Koester, J. Magerlein, R. Puri, A. Young, Interconnects in the third dimension: design chal- lenges for 3D ICs, in Proceedings of 44th Annual Conference on Design Automation (2007), pp. 562-567
63. C. Ferri, S. Reda, I. Bahar, Parametric yield management for 3D ICs: models and strategies for improvement. ACM J. Emerg. Technolog. Comp. Syst. 4, 22 (2008)
64. M. Hogan, D. Petranovic, Robust verification of 3D-ICs: pros, cons and recommendations, in 3D System Integration, 2009, 3DIC 2009 (2009)
65. T. Bandyopadhyay, K. Han, D. Chung, R. Chatterjee, M. Swaminathan, R. Tummala, Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects. IEEE Trans. Compon. Packag. Manuf. Technol. 1(6), 893-903 (2011)
66. ALLVIA-The First Through-Silicon Via (TSV) Foundry, http://www.allvia.com/
67. H. Yu, J. Ho, L. He, Simultaneous power and thermal integrity driven via stapling in 3D ICs, Electrical Engineering Department, UCLA, 2009
68. K.C. Chillara, J. Jang, W.P. Burleson, Robust signaling techniques for through silicon via bundles, in GLSVLSI'11, May 2011
69. P.E. Garrou, E.J. Vardaman, P.D. Franzon, Through silicon via technology: the ultimate market for 3D interconnect, Tech Search International, Jan 2008
70. http://www.itrs.net
71. L. Cadix, C. Fuchs, M. Rousseau, P. Leduc, H. Chaabouni, A. Thuaire, M. Brocard, A. Valentian, A. Farcy, C. Bermond, N. Sillon, B. Fléchet, P. Ancey, Integration and frequency dependent parametric modeling of through silicon via involved in high density 3D chip stacking
72. http://www.eda.ncsu.edu/wiki/freePDK
73. R. Weerasekera, L.-R. Zheng, D. Pamunuwa, H. Tenhunen, Extending systems-on-chip to the third dimension: performance, cost and technological trade-off, in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2007, pp. 212-219
74. T. Szirtes, Applied Dimensional Analysis and Modeling. (McGraw-Hill, New York, 1997)
75. K.J. Han, Electromagnetic Modeling of Interconnections in Three-Dimensional Integration. PhD Dissertation, Georgia Institute of Technology, Aug 2009
76. Ankur et al., New Paradigm in IC-Package Interconnections by Reworkable Nano-Interconnects, 2004 Electronic Components and Technology Conference, 2004, pp. 451-460
77. T. Bandyopadhyay, R. Chatterjee, D. Chung, M. Swaminathan, R. Tummala, Electrical Modeling of Through Silicon and Package Vias, in 3D System Integration. 3DIC 2009. IEEE International Conference, 2009
78. C. Xu, H. Li, R. Suaya, Compact AC Modeling and Analysis of Cu, W, and CNT based Through-Silicon Vias (TSVs) in 3-D ICs, in IEDM09-521, 2009
79. M. Stucchi, K.D. Meyer, W. Dehaene, S.G. Katti, Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs, IEEE Transactions on Electron Devices, vol. 57, no. 1, Jan 2010
80. Y.L. Chow, M.M.A. Salama, A Simplified Method for Calculating the Substation Grounding Grid Resistance, Power Delivery, IEEE Transactions, April 1994, pp. 736-742
81. http://www.ansoft.com/products/si/hfss
82. http://www.ansoft.com/products/si/q3d extractor
83. R. Fillion, C. Woychik, T. Zhang, D. Bitting, Embedded chip build-up using fine line interconnect, in Proceeding of the 57th Electronics Components and Technology Conference, 2007
84. A. Ito, A Voltage Dependent Capacitance Model Including Effects of Manufacturing Process Variabilities on Voltage Coefficients, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 14, no. 9, Sept 1995
85. http://en.wikipedia.org/wiki/Taylor_series
86. http://www.matlab.com
87. Ansys, (n.d.), http://www.ansoft.com/products/si/q3dextractor. Accessed 2013
88. Agilent Technologies, (n.d.), http://www.home.agilent.com/agilent
89. Mentor Graphics, Eldo classic: foundry certified SPICE accurate circuit simulation (n.d.), http://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo
90. T. R. Kuphaldt, Time constant calculations (n.d.), www.ibiblio.org/kuphaldt/socratic/output/time2.pdf
91. L.H. Bomholt, P. Regli, T.O. Korner, W. Fichtner, Combination of Device Simulation with Computational Electromagnetics (IEEE, New York, 1998)
92. G. Wang, Coupled electromagnetic and device level investigations of metal-insulator-semiconductor interconnects, Ph.D. dissertation, Department of Science and Computers, Stanford University, 2001
93. F. M. Rotella, Equations for mixed circuit/device stimulation (n.d.), http://www-tcad.stanford. edu/~fmr/research/mixedmode/equations.html
94. Synopsis Inc., Sentaurus Device User Guide, Ver. A-2008.09 (Synopsis Inc., Mountain View, 2008 Sep)
95. R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits, DATE, 2010
96. M. Grange, R. Weerasekera, D. Pamunuwa, Optimal signaling techniques for through silicon vias in 3-D integrated circuit packages, in Proceedings of IEEE Electrical Performance of Electronic Packaging and Systems, 2010
97. H. Sane, Power supply noise analysis for 3D ICs using through silicon via, Master's Thesis. ECE Department Georgia Institute of Technology, 2010
98. M. Grange, R. Weerasekera, D. Pamunuwa, H. Tenhunen, Exploration of through silicon via interconnect parasitics for 3-dimensional integrated circuits, DATE, 2009
99. D. Chen, W. Chiou, M. Chen, T. Wang, K. Ching et al., Enabling 3D-IC foundry technologies for 28 nm node and beyond: through silicon-via integration with high throughput die-to-wafer stacking, in Proceedings of IEEE International Electron Devices Meeting, Dec 2009, pp. 1-4
100. J.S. Pak, C. Ryu, J. Kim, Multi-stacked through-silicon-via effects on signal integrity and power integrity for application of 3-dimensional stacked-chip-package, URSIGA, 2008
101. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, J. Kim, High frequency electrical model of through wafer via for 3-D stacked chip packaging, Electronics System-integration Technology Conference, Sept 2006, vol. 1, pp. 215-220
102. J. Rosenfeld, E.G. Friedman, On-chip DC-DC converters for three-dimensional ICs. 10th international symposium on quality electronic design, IEEE 2009
103. C.P. Yue, S.S. Wong, Physical modeling of spiral inductors on silicon. IEEE Trans. Electron. Devices 47, 560-568 (2000)
104. M. Wang, J. Li, K. D. T. Ngo, H. Xie, A novel integrated power inductor in silicon substrate for ultra-compact power supplies. 21st IEEE Applied Power Electronics Conference, APEC 2010
105. D.W. Lee, K.P. Hwang, S.X. Wang, Design and fabrication of integrated solenoid inductors with magnetic cores. 58th Electronic Components and Technology Conference (ECTC), 2008
106. A. Zolfaghari, A. Chan, B. Razavi, Stacked inductors and transformers in CMOS technology. IEEE J. Solid-State Circuits 36(4), 620-628 (2001)
107. T.S. Horng, K.C. Peng, J.K. Jau, Y.S. Tsai, S-parameter formulation of quality factor for a spiral inductor in generalized two-port configuration. IEEE Trans. Microw. Theory Techn. 51(11), 2197-2202 (2003)
108. M. Danesh, J.R. Long, Differentially driven symmetric microstrip inductors. IEEE Trans. Microw. Theory Techn. 50(1), 332-341 (2002)
109. C.C. Tang, C.H. Wu, S.I. Liu, Miniature 3-D inductors in standard CMOS process. IEEE J. Solid-State Circuits 37(4), 471-480 (2002)
110. S.S. Mohan, M.D.M. Hershenson, S.P. Boyd, T.H. Lee, Simple accurate expressions for planar spiral inductances. IEEE J. Solid-State Circuits 34(10), 1419-1420 (1999)
111. A. Alphones, W.K. Yee, Optimization of spiral inductor on silicon. IEEE Microwave Symposium Digest, 2006
112. J.N. Burghartz, K.A. Jenkins, M. Soyuer, Multilevel spiral inductors using VLSI interconnect technology. IEEE Electron Device Lett. 17(9), 428-430 (1996)
113. S. Kodali, D.J. Allstor, Asymmetric miniature 3D inductor. IEEE Circuits Systems, 2003
114. A. Sutono, A. Pham, J. Laskar, W.R. Smith, Development of three dimensional ceramicbased MCM inductors for hybrid RF microwave applications. IEEE Radio Frequency Integrated Circuits Symposium,1999
115. J.M. López, J. Samitier, C. Cané, P. Losantos, J. Bausells, Improvement of the quality factor of RF integrated inductors by layout optimization. IEEE Trans. Microw. Theory Techn. 48(1), 76-83 (2000)
116. M. Ballicchia, S. Orcioni, Design and modeling of optimum quality spiral inductors with regularization and Debye approximation. IEEE Trans. Comput.-Aided Des Integr. Circuits Syst. 29(11), 1669 (2010)
117. J. Chen, J.J. Liou, On-chip spiral inductors for RF applications: An overview. J. Semicond Technol. Sci. 4(3), 149-167 (2004)
118. W. Yu, J.W. Bandler, Optimization of spiral inductor on silicon using space mapping. Microwave Symposium Digest, 2006
119. D.R. Pehlke, A. Burstein, M.F. Chang, Extremely high-Q tunable inductor for Si-based RF integrated circuit applications. Electron Devices Meeting, IEDM'97
120. N. Bheema, A.N. Chandorkar, 3D inductor for RF applications. Int. J. Microw. Opt. Technol. 3(4), 179-181 (2008)
121. N.B. Rao, A.N. Chandorkar, Optically tunable spiral inductor for RF applications. The Ninth International Conference on Communications Systems, ICCS 2004
122. L.F. Tiemeijer, R.J. Havens, Y. Bouttement, H.J. Pranger, The impact of an aluminium top layer on inductors integrated in an advanced CMOS copper backend. IEEE Electron. Device Lett. 45(11), 722-724 (2004)
123. T. Kuroda, Lower cost alternative to TSV using ThruChip interface (TCI) (Keynote). DATE 2011 Workshop on 3D Integration, March 2011
124. J. Xu, S. Mick, J. Wilson, L. Luo, K. Chandrasekar, E. Erickson, P.D. Franzon, AC coupled interconnect for dense 3-D ICs. IEEE Trans. Nucl. Sci. 51(5), 2156-2160 (2004)
125. E. J. Marinissen, D.Y. Lee, J.P. Hayes, C. Sellathamby, B. Moore, S. Slupsky, L. Pujol, Contactless testing: possibility or pipe-dream? EDAA, 2009
126. A. More, B. Taskin, Wireless interconnects for inter-tier communication on 3D ICs. IEEE Microwave Conference (EuMC), 2010
127. E. Culurciello, A.G. Andreou, Capacitive coupling of data and power for 3D silicon-on-insulator VLSI. IEEE International Symposium on Circuits and Systems, ISCAS 2005
128. T. Zhang, R. Micheloni, G. Zhang, Z.R. Huang, J.J. Lu, 3-D data storage, power delivery, and RF/optical transceiver case studies of 3-D integration from system design perspectives. IEEE Proc 97(1), 161-174 (2009)
129. K. Kawasaki, Y. Akiyama, K. Komori, M. Uno, H. Takeuchi, T. Itagaki, Y. Hino, Y. Kawasaki, K. Ito, A. Hajimiri, A millimeter-wave intra-connect solution. IEEE J. Solid-State Circuits 45(12), 2655-2666 (2010)
130. S. Hu, L. Wang, Y.Z. Xiong, J. Shi, B. Zhang, D. Zhao, T.G. Lim, X. Yuan, Millimeter-wave/THz passive components design using through silicon via (TSV) technology. Electronic Components and Technology Conference, 2010
131. M. Duplessis, O. Tesson, F. Neuilly, J.R. Tenailleau, P. Descamps, Physical implementation of 3D integrated solenoids within silicon substrate for hybrid IC applications. Proceedings of the 39th European Microwave Conference, 2009
132. B. Zhang, Y.Z. Xiong, L. Wang, S. Hu, J. Shi, Y.Q. Zhuang, L.W. Li, X. Yuan, 3D TSV transformer design for DC-DC/AC-DC converter. Electronic Components and Technology Conference, 2010
133. H. Lehpamer, RFID Design Principles. (Artech House Inc., Norwood, 2008)
134. A. More, B. Taskin, Simulation based study of on-chip antennas for a reconfigurable hybrid 3D wireless NoC. The Proceedings of the IEEE International SoC Conference (SOCC), September 2010
135. T. Kuroda, N. Miura, Perspective of low-power and high-speed wireless inter-chip communications for SiP integration. Proceedings of the 32nd European Solid-State Circuits Conference, ESSCIRC 2006
136. R.R. Harrison, Designing efficient inductive power links for implantable devices. IEEE International Symposium on Circuits and Systems, ISCAS 2007
137. S. Han, D.D. Wentzloff, Wireless power transfer using resonant inductive coupling for 3D integrated ICs. 3DIC, 2010
138. S. Han, D. D. Wentzloff, 0.61 W/mm2 resonant inductively coupled power transfer for 3DICs. CICC, 2012
139. B. Razavi, Design of millimeter-wave CMOS radios: A tutorial. IEEE Trans. Circuits Syst. Part I 56(1), 4-16 (2009)
140. D.M. Pozar, Microwave Engineering. (Wiley, New York, 2005)
141. J.X. Chewn, C.Y. Cheung, Q. Xue, Integrated bandpass filter based on double-sided parallel line with an integrated conductor plane. Asian Pacific Microwave Conference, Bangkok, Thailand, December 2007
142. Jia-Sheng Hong, M.J. Lancaster, Microstrip Filters for RF/Microwave Applications. (Wiley, New York, 2001)
143. http://en.wikipedia.org/wiki/Constant_k_filter. Accessed 2013
144. T. Bandyopadhyay, K. Han, D. Chung, R. Chatterjee, M. Swaminathan, R. Tummala, Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects. IEEE Trans. Compon. Packag. Manuf. Technol. 1(6), 893-903 (2011)
145. A. Papanikolaou, D. Soudris, Three Dimensional System Integration: IC Stacking Process and Design. (Springer, New York, 2011)
146. K. Yoon, G. Kim, W. Lee, T. Song, J. Lee, H. Lee, K. Park, J. Kim, Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer. Electronics Packaging Technology Conference,11th, pp. 702-706, IEEE, Singapore, 9-11 Dec 2009
147. M. Rousseau, M-A. Jaud, P. Leduc, A. Farcy, A. Marty, Impact of substrate coupling induced by 3D-IC architecture on advanced CMOS technology. European Microelectronics and Packaging Conference, IEEE, Rimini, Italy, 15-18 June 2009
148. H. Chaabouni, M. Rousseau, P. Leduc, A. Farcy, R. El-Farhane, A. Thuaire, G. Haury, A. Valentian, G. Billiot, M. Assous, F. De Crecy, J. Cluzel, A. Toffoli, D. Bouchu, L. Cadix, T. Lacrevaz, P. Ancey, N. Sillon, B. Flechet, Investigation on TSV impact on 65 nm CMOS devices and circuits. Electron Devices Meeting (IEDM), IEEE, San Francisco, 6-8 Dec 2010
149. N.H. Khan, S.M. Alam, S. Hassoun, Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. Conference on 3D System Integration, IEEE, San Francisco, 28-30 Sept 2009
150. M. Rousseau, M-A. Jaud, P. Leduc, A. Farcy, A. Marty, Through-silicon via based 3D IC technology: Electrostatic simulations for design methodology. IMAPS, Device Packaging Conference, Phoenix, 2008
151. P-J. Yang, P-T. Huang, W. Hwang, Substrate noise suppression technique for power integrity of TSV 3D integration. Circuits and Systems (ISCAS), 2012 IEEE International Symposium, Seoul, 20-23 May 2012
152. J. Cho, J. Shim, E. Song, J.S. Pak, J. Lee, H. Lee, K. Park, J. Kim, Active circuit to through silicon via (TSV) noise coupling. Electrical Performance of Electronic Packaging and Systems, IEEE, Portland, 19-21 Oct 2009
153. C. Xu, R. Suaya, K. Banerjee, Compact modeling and analysis of through-si-via-induced electrical noise coupling in three-dimensional ICs. IEEE Transactions on Electron Devices, Vol. 58, No. 11, Nov 2011
154. S. Uemura, Y. Hiraoka, T. Kai, S. Dosho, Isolation techniques against substrate noise coupling utilizing through silicon via (TSV) process for RF/mixed-signal SoCs. IEEE J. Solid- State Circuits 47(4) (April 2012)
155. N.H. Khan, S.M. Alam, S. Hassoun, Mitigating TSV-induced substrate noise in 3-D ICs using GND Plugs. 12th International Symposium on Quality Electronic Design (ISQED), IEEE, Santa Clara, 14-16 March 2011
156. E. Salman, Noise coupling due to through silicon vias (TSVs) in 3-D integrated circuits. IEEE International Symposium on Circuits and Systems, Rio de Janeiro, 15-18 May 2011
157. Silvaco International (Atlas User's Manual, USA, 2008), www.silvaco.com. Accessed 2012
158. G. Veronis, Y.C. Lu, R.W Dutton, Modeling of wave behavior of substrate noise coupling for mixed-signal IC design. Proceedings of the International Symposium on Quality Electronic Design, pp. 303-308, Stanford University, CA, 2004
159. D.K. Su, M.J. Loinaz, S. Masui, B.A. Wooley, Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits. IEEE J. Solid-State Circuits 28, 420- 430 (1993)
160. T. Blalack, J. Lau, F.J.R. Clément, B.A. Wooley, Experimental results and modeling of noise coupling in a lightly doped substrate. International Electron Devices Meeting, IEDM '96 Tech. Dig., pp. 623-626, San Fransisco, 8-11 Dec 1996
161. X. Aragonès, A. Rubio, Experimental comparison of substrate noise coupling using different waver types. IEEE J. Solid-State Circuits 34, 1405-1409 (1999)
162. H. Wang, J. Kim, Y. Shi, J. Fan, The effects of substrate doping density on the electrical performance of through-silicon-via (TSV). Asia-Pacific Symposium & Exhibition on Electromagnetic Compatibility, Jeju Island, 16-19 May 2011
163. BSIM3v3 Manual Copyright © 1995, 1996, UC Berkeley
164. L. Yu, H. Yang, J. Zhang, W. Wang, Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC. IEEE/IFIP 19th international conference on VLSI and system-on-chip, 2011
165. L. Yu, H. Yang, T.T. Jing, M. Xu, R. Geer, W. Wang, Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs. IEEE, 2010
166. A. Gupta, B.C. Kim, S. Kannan, S.S. Evana, L. Li, Analysis of CNT based 3D TSV for emerging RF applications. Electronic components and technology conference, 2011
167. B. Kim, S. Kannan, A. Gupta, S. Noh, L. Li, Characterization of high performance CNT-based TSV for radar applications. IEEE 13th electronics packaging technology conference, 2011
168. S. Kannan, B. Kim, A. Gupta, S. Noh, L. Li, Characterization of high performance CNTbased TSV for high-frequency RF applications. Adv. Mater. Res. 1(1) (2012)
169. T. Wang, K. Jeppson, N. Olofsson, E. Campbell, J. Liu, Through silicon vias filled with planarized carbon nanotube bundles. IOPscience, Nanotech. 20(48), (2009)
170. A. Gupta, S. Kannan, B. Kim, F. Mohammed, B. Ahn, Development of novel carbon nanotube TSV technology. IEEE electronic components and technology conference, 2010
171. S. Hassan, M. Asghar, Limitation of silicon based computation and future prospects. Second international conference on communication software and networks, 2010
172. N. Arora, B.P. Singh, T. Sharma, K.G. Sharma, Adiabatic and standard CMOS interfaces at 90 nm technology. WSEAS Trans. Circuits Syst. 9(3) (2010)
173. J.C. Garcia, J.A. Montiel, S. Nooshabadi, A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss. IEEE, 2008
174. P. Asimakopoulos, G. Van der Plas, A. Yakovlev, P. Marchal, Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. IEEE, 2009
175. P.D. Khandekar, S. Subbaraman, A.V. Chitre, Implementation and analysis of quasi-adiabatic inverters. IMECS, 2010
176. H. Mahmoodi, V. Tirumalashetty, M. Cooke, K. Roy, Ultra low-power clocking scheme using energy recovery and clock gating. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(1), 33-44 (2009)
177. P. Sreenivasulu, M.V. Narasimha, G.V.K. Varaprasad, Design and analysis of low power full adder using adiabatic technique. Int. J. Emerg. Technol. Adv. Eng. 2(6) (2012)
178. S. Mandavilli, P. Paramahans, An efficient adiabatic circuit design approach for low power applications. Int. J. Recent Trends Eng. 2(1) (2009)
179. N. Anuar, Y. Takahashi, T. Sekine, Adiabatic logic versus CMOS for low power applications. IEEE, 2010
180. N. Anuar, Y. Takahashi, T. Sekine, Two phase clocked adiabatic static logic circuit: a proposal for digital low power applications. Proc. IEICE General Conference, March 2009, p. 102
181. R. Kumbhare, J. Kanungo, A.K. Saxena, S. Dasgupta, Design of an ultra low power clock gating D flip-flop using quasi-static energy recovery logic. Microelectron. Solid State Electron. 1(1), 9-14 (2012)
182. H.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C.S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, S.L. Wright, 3D silicon integration. Electronic components and technology conference, 2008
183. Y. Xie, Processor architecture design using 3D integration technology. 23rd international conference on VLSI design, 2010
184. E.J. Marinissen, Y. Zorian, Testing 3D chips containing through-silicon vias. International test conference, 2009
185. T.M. Bauer, S.L. Shinde, J.E. Massad, D.L. Hetherington, Front end of line integration of high density, electrically isolated, metallized through silicon vias. Electronic components and technology conference, 2009
186. D.Y. Chen, W.C. Chiou, M.F. Chen, T.D. Wang, K.M. Ching, Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking. IEEE, 2009
187. A. Klumpp, P. Ramm, R. Wieland, 3D-integration of silicon devices: a key technology for sophisticated products. Date, 2010
188. C. Laviron, B. Dunne, V. Lapras, P. Galbiati, D. Henry, F. Toia, S. Moreau, R. Anciant, C.B. Manquat, N. Sillon, Via first approach optimisation for through silicon via applications. Electronic components and technology conference, 2009
189. R. Weerasekera, M. Grange, D. Pamunuwa, On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits. Date, 2010
190. M. Koyanagi, T. Fukushima, T. Tanaka, Three-dimensional integration technology and integrated systems. IEEE, 2009
191. http://www.suss.com/markets/3d-integration/tsv-manufacturing.html. Accessed 2012
192. http://www.austriamicrosystems.com/. Accessed 2012
193. Y. Civale, D.S. Tezcan, H.G.G. Philipsen, P. Jaenen, R. Agarwal, F. Duval, P. Soussan, Y. Travaly, E. Beyne, Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. IEEE, 2009
194. M.J. Wolf, P. Ramm, A. Klumpp, H. Reichl, Technologies for 3D wafer level heterogeneous. DTIP, 2008
195. S.Q. Gu, U. Ray, Y. Li, A. Chandrasekaran, B. Henderson, M. Nowak, 3D TSV integration technology challenges for high volume production from fabless supply chain aspect. IEEE, 2010
196. C. Huyghebaert, J.V. Olmen, Y. Civale, A. Phommahaxay, A. Jourdain, S. Sood, S. Farrens, P. Soussan, Cu to Cu interconnect using 3D-TSV and Wafer to Wafer thermo compression bonding. IEEE, 2010