Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs

Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011

Volumn , Issue , 2011, Pages 751-756

  Khan, Nauman H ^a   Alam, Syed M ^b   Hassoun, Soha ^a  

^a Tufts University   (United States)

^b Everspin Technologies   (United States)

Author keywords

3 D integrated circuit (IC); 3 D integration; substrate noise; through silicon via (TSV)

Indexed keywords

3-D ICS; 3-D INTEGRATED CIRCUIT (IC); 3-D INTEGRATION; ACTIVE DEVICES; DIELECTRIC LINERS; DIELECTRIC THICKNESS; GROUND PLANES; KEEP-OUT-ZONE; NOISE ISOLATION; NOISE MITIGATION; PERFORMANCE DEGRADATION; SUBSTRATE NOISE; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV);

ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; THREE DIMENSIONAL; TUNGSTEN;

SUBSTRATES;

EID: 79959276395     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2011.5770813     Document Type: Conference Paper

References (15)

1. Ansoft-Q3D Extractor. http://www.ansoft.com/products/si /q3dextractor/.
2. International Technology Roadmap for Semiconductors. http://www.itrs.net/ Links/2009ITRS/Home2009.htm.
3. A. A. Kusha, M. Nagata, N. K. Verghese, and D. J. Allstot, Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation Proceedings of the IEEE, vol. 94, no. 12, pp. 2109-2138, Dec. 2006
4. B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb. "Die Stacking (3D) Microarchitecture," MICRO 39: Proceedings of the 39th Annual IEEE/AC M International Symposium on Microarchitecture, pp 469-479, 2006. (Pubitemid 351337019)
5. J. Cho J. Shim E. Song, J. S. Pak, J. Lee, H. Lee, K. Park, and J. Kim. Active Circuit to Through Silicon Via (TSV) Noise Coupling IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, pp 97-100, 2009.
6. F. Clment. "Substrate Noise Coupling Analysis in Mixed-Signal ICs September 2001.
7. W.R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A.M. Sule, M. Steer, and P.D. Franzon. "Demystifying 3D ICs: The Pros and Cons of Going Vertical," Design & Test of Com puters, IEEE, vol. 22, no. 6, pp 498-510, Nov. 2005. (Pubitemid 41715957)
8. G. V. Plas, P. Limaye, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, K. Guruprasad, D. Velenis, D. Shinichi, V. Cherman, B. Vandevelde, V. Simons, I. D. Wolf, R. Labie, D. Perry, S. Bronckers, N. Minas, M. Cupac, W. Ruythooren, J. V. Olmen, A. Phommahaxay, M. P. Broeck, A. Opdebeeck, M. Rakowski, B. Wachter, M. Dehan, M. Nelis, R. Agarwal, W. Dehaene, Y. Travaly, P. Marchal, and E. Beyne. Design Issues and Considerations for Low-Cost 3D TSV IC Technology," IEEE International Solid- State Circuits Conference, pp 148-149, 2010.
9. S. W. Ho, S. W. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J.H. Lau. High RF Performance TSV Silicon Carrier for High Frequency Application," E lectronic Components and Technology Conference, pp 1946-1952, 2008.
10. T. Jiang and S. Luo. "3D Integration-Present and Future " 10th Electronics Packaging Technology Conference, pp 373-378, 2008.
11. N. H. Khan, S. M. Alam, and S. Hassoun. Through-Silicon Via (TSV)-induced Noise Characterization and Noise Mitigation Using Coaxial TSVs", IEEE International Conference on 3D System Integration, pp 1-7, Sept. 2009.
12. H. Kikuchi, Y. Yamada, A. M. Ali, J. Liang, T. Fukushima, T. Tanaka, and M. Koyanagi. "Tungsten Through-Silicon Via Technology for Three-Dimensional LSIs," Japanese Journal of Applied Physics, April 2008.
13. J.U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-J ayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B.C. Webb, and S. L. Wright. Three-Dimensional Silicon Integration," IBM Journal of Research and Development, vol.52, no.6, pp553-569, Nov. 2008.
14. M. Motoyoshi. "Through-Silicon Via (TSV) Proceedings of the IEEE, vol. 97, no. 1, pp 43-48, January 2009.
15. M. Rousseau, M.A. Jaud, P. Leduc, A. Farcy, and A. Marty. Impact of Substrate Coupling Induced by 3D-IC Architecture on Advanced CMOS Technology," Microelectronics and Packaging Conference, pp 1-5, 2009.