Enabling 3D-IC foundry technologies for 28 nm node and beyond: Through-silicon-via integration with high throughput die-to-wafer stacking

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2009, Pages

  Chen, D Y ^a   Chiou, W C ^a   Chen, M F ^a   Wang, T D ^a   Ching, K M ^a   Tu, H J ^a   Wu, W J ^a   Yu, C L ^a   Yang, K F ^a   Chang, H B ^a   Tseng, M H ^a   Hsiao, C W ^a   Lu, Y J ^a   Hu, H P ^a   Lin, Y C ^a   Hsu, C S ^a   Shue, Winston S ^a   Yu, C H ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; CMOS CHIPS; FOUNDRY TECHNOLOGY; HIGH DENSITY; HIGH THROUGHPUT; IC PROCESS; INTEGRATION SCHEME; KEY PROCESS; THROUGH-SILICON-VIA; WAFER STACKING;

CMOS INTEGRATED CIRCUITS; DIES; ELECTRON DEVICES; FOUNDRY PRACTICE; LEAKAGE CURRENTS; NANOTECHNOLOGY; THREE DIMENSIONAL;

SILICON WAFERS;

EID: 77952402732     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2009.5424350     Document Type: Conference Paper

References (5)

1. S. Borkar et al., Symp. VLSI Tech., 2009, pp. 58.
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4. P. R. Morrow et al, IEEE Electron Device Lett., 2006, pp.335.
5. N. Tanaka et al, Electronics System Integration Technology Conf., 2006, pp.394.