Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Microelectronics Journal

Volumn 41, Issue 1, 2010, Pages 9-16

  Savidis, Ioannis ^a,b   Alam, Syed M ^c   Jain, Ankur ^d   Pozder, Scott ^a   Jones, Robert E ^a   Chatterjee, Ritwik ^a,e  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b University of Rochester   (United States)

^c Everspin Technologies   (United States)

^d MOLECULAR IMPRINTS INC   (United States)

^e GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3D integration; Electrical characterization; IO delay; TSV; Via parasitics; Vias

Indexed keywords

3-D INTEGRATED CIRCUIT; 3-D INTEGRATION; CHIP PERFORMANCE; COMPREHENSIVE ANALYSIS; D-CONNECTION; DESIGN TOOL; ELECTRICAL CHARACTERISTIC; ELECTRICAL CHARACTERIZATION; ELECTRICAL MODELING; ELECTRICAL PROPERTY; FLOOR-PLANNING; GLOBAL WIRES; GROUNDED SUBSTRATES; INDUCTIVE COUPLINGS; MICROCONNECTS; PARASITICS; SYSTEM LEVELS; TECHNOLOGY NODES; TECHNOLOGY SCALING; THROUGH SILICON VIAS;

COMPUTER CRIME; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC PROPERTIES; INTERCONNECTION NETWORKS; WIRE;

THREE DIMENSIONAL;

EID: 75149122784     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2009.10.006     Document Type: Article

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