3-D ICs: A novel chip design for improving deep-submieroraeter interconnect performance and systems-on-chip integration and systems-on-chlp integration

Proceedings of the IEEE

Volumn 89, Issue 5, 2001, Pages 602-632

  Banerjee, Kaustav ^a   Souri, Shukri J ^a   Kapur, Pawan ^a   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

Author keywords

3 d ICs; Heterogeneous integration; Interconnect performance; Optical i os; Power dissipation; System interconnects; System on a chip design; VLSI design

Indexed keywords

EID: 33747566850     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.929647     Document Type: Article

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