Through silicon via (TSV) equalizer

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS '09

Volumn , Issue , 2009, Pages 13-16

  Kim, Joohee ^a   Song, Eakhwan ^a   Cho, Jeonghyeon ^a   Pak, Jun So ^a   Lee, Junho ^b   Lee, Hyungdong ^b   Park, Kunwoo ^b   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3-DIMENSIONAL; HIGH-SPEED DIGITAL SIGNALS; THROUGH-SILICON-VIA; VERTICAL INTERCONNECTIONS;

ELECTRONICS PACKAGING; INTERSYMBOL INTERFERENCE; OHMIC CONTACTS;

THREE DIMENSIONAL;

EID: 74549171498     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2009.5338488     Document Type: Conference Paper

References (9)

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9. Ryu, C., Lee, J., Lee, H., Lee, K., Oh, T. and Kim, J., "High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging," Electronics System Integration0 Technology Conference, 2006.