Interconnects in the third dimension: Design challenges for 3D ICs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 562-567

  Bernstein, Kerry ^a   Andry, Paul ^a   Cann, Jerome ^b   Emma, Phil ^a   Greenberg, David ^a   Haensch, Wilfried ^a   Ignatowski, Mike ^a   Koester, Steve ^a   Magerlein, John ^a   Puri, Ruchir ^a   Young, Albert ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

3D; Bandwidth; Chip stack; Hierarchical memory; Interconnect; Latency; Silicon carrier; Through wafer via

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; HIERARCHICAL SYSTEMS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS;

3D CHIP TECHNOLOGIES; SILICON CARRIERS; TRANSISTOR PERFORMANCE GROWTH;

INTEGRATED CIRCUIT LAYOUT;

EID: 34547322811     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375227     Document Type: Conference Paper

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