High frequency electrical model of through wafer via for 3-D stacked chip packaging

ESTC 2006 - 1st Electronics Systemintegration Technology Conference

Volumn 1, Issue , 2006, Pages 215-220

  Ryu, Chunghyun ^a   Lee, Jiwang ^a   Lee, Hyein ^a   Lee, Kwangyong ^b   Oh, Taesung ^b   Kim, Joungho ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b Hong Ik University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; CIRCUIT SIMULATION; EQUIVALENT CIRCUITS; PARAMETER ESTIMATION; SILICON WAFERS;

CIRCUIT MODELS; ELECTRICAL MODELS; PARAMETER OPTIMIZATION; STACKED CHIP PACKAGING;

SEMICONDUCTOR DEVICE MODELS;

EID: 42549142869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESTC.2006.280001     Document Type: Conference Paper

References (6)

1. S. Linder, H. Baltes, F. Gnaedinger, and E. Doering, "Fabrication technology for wafer through-hole hinterconnections and three-dimensional stacks of chips and wafers", in Proc. MEMS, 1994, pp. 349-354.
2. M. Koyanagi, H. Kurino, K. Lee, K. Sakmicrona, N. Miyakawa, H. Itani, "Future System-on-Silicon LSI Systems", IEEE Micro, Vol. 18, No. 4, July-Aug. 1998, pp 17
3. K. Takahashi, M. Hoshino, H. Yonemura, M. Tomisaka, M. Sunohara, M. Tanioka, T. Sato, K. Kojima, H. Terao, "Development of Advanced 3-D Chip Stacking Technology with Ultra-Fine Interconnection", Proc. 51st Electronic Components and Technology Conf., Orlando, FL., May 2001, pp
4. th International Conference on Electronic Packaging Technology, pp 57-60, Sept. 2005
5. L. L. W. Leung, and K. J. Chen, "Microwave Characterization and Modeling of High Apect Ratio Through-Wafer Interconnect Vias in Silicon Substrates", IEEE Transation on Microwave Theory and Techniques, " Vol. 53, No. 8, pp 2472-2480, August 2005
6. S. Ahn, J. Lee, J. Lee, J. Kim, W. Ryu, B.-H. Kmicron, H.-S. Choi, C. K. Yoon, and J. Kim, "Over GHz Electrical Circuit Model of a High-Density Multiple Line Grid Array(MLGA) Interposer, IEEE transaction on advanced packaging, Vol. 26.