Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 6, 2011, Pages 893-903

  Bandyopadhyay, Tapobrata ^a   Han, Ki Jin ^b   Chung, Daehyun ^c   Chatterjee, Ritwik ^d   Swaminathan, Madhavan ^e   Tummala, Rao ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c NVIDIA   (United States)

^d McGarry Bair PC   (United States)

^e GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3 D integration; interconnection modeling; parametric study; power distribution network; through silicon via; variable capacitance

Indexed keywords

3-D INTEGRATION; BUILDING BLOCKES; CAPACITANCE EFFECT; DESIGN GUIDELINES; ELECTRICAL MODELING; HETEROGENEOUS INTEGRATION; MATERIAL PARAMETER; MEASUREMENT RESULTS; METAL OXIDE SEMICONDUCTOR; MICROELECTRONIC SYSTEMS; PARAMETRIC ANALYSIS; PARAMETRIC STUDY; POWER DISTRIBUTION NETWORK; SYSTEM SIZE; THROUGH SILICON VIAS; THROUGH-SILICON-VIA; VARIABLE CAPACITOR; WIRING DELAY;

CAPACITANCE; ELECTRIC NETWORK ANALYSIS; INTEGRATION; MICROELECTRONICS;

THREE DIMENSIONAL;

EID: 84857454206     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2011.2120607     Document Type: Article

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