Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits

2009 IEEE International Conference on 3D System Integration, 3DIC 2009

Volumn , Issue , 2009, Pages

  Weerasekera, Roshan ^a   Grange, Matt ^a   Pamunuwa, Dinesh ^a   Tenhunen, Hannu ^b   Zheng, Li Rong ^b  

^a LANCASTER UNIVERSITY   (United Kingdom)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; COMPACT MODELLING; COUPLING TERMS; CRITICAL ISSUES; DELAY VARIATION; DESIGN SPACE EXPLORATION; ELECTRICAL CHARACTERISTIC; ELECTRICAL CIRCUIT MODELS; PARASITIC PARAMETER; PARASITICS; PERCENTAGE POINTS; PERFORMANCE EVALUATION; PERFORMANCE MODELING; REDUCED ORDER; SELF-CONSISTENT EQUATIONS; SIGNAL INTEGRITY; SPECTRE SIMULATIONS; SWITCHING PATTERNS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

CROSSTALK; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; SIMULATORS; SPACE RESEARCH;

THREE DIMENSIONAL;

EID: 70549084864     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2009.5306541     Document Type: Conference Paper

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