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Volumn , Issue , 2009, Pages 97-100

Active circuit to through silicon via (TSV) noise coupling

Author keywords

[No Author keywords available]

Indexed keywords

3-DIMENSIONAL; ACTIVE CIRCUITS; COUPLING MODELS; COUPLING NOISE; EQUIVALENT LUMPED CIRCUITS; GUARD-RINGS; NOISE COUPLING; NOISE SOURCE; S PARAMETERS; SHIELDING TECHNIQUES; SILICON SUBSTRATES; STRUCTURAL PARAMETER; SUBSTRATE NOISE COUPLING; THROUGH-SILICON-VIA; TRANSMISSION-LINE MATRIXES;

EID: 74549172091     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2009.5338469     Document Type: Conference Paper
Times cited : (50)

References (7)
  • 1
    • 51249113887 scopus 로고    scopus 로고
    • Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation
    • May
    • J. Pak, C. Ryu, J. Kim, "Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation", Electromagnetic Electronic Materials and Packaging, 2007.Conf., May.2008 pp.351-354
    • (2008) Electromagnetic Electronic Materials and Packaging, 2007.Conf , pp. 351-354
    • Pak, J.1    Ryu, C.2    Kim, J.3
  • 4
    • 42549142869 scopus 로고    scopus 로고
    • High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging
    • Sept
    • C. Ryu, J. Lee, K. Lee, T. Oh, J. Kim, "High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging", Electronics Systemintegration Technology Conf.,Sept.2006,vol 1,pp.215-220.
    • (2006) Electronics Systemintegration Technology Conf , vol.1 , pp. 215-220
    • Ryu, C.1    Lee, J.2    Lee, K.3    Oh, T.4    Kim, J.5
  • 5
    • 0029500058 scopus 로고    scopus 로고
    • F. B. J. Leferink, Inductance calculations: methods and equations, in Proc. IEEE Int. Symp. Electromag. Compat., Atlanta, GA, 1995, pp.16-22.
    • F. B. J. Leferink, "Inductance calculations: methods and equations," in Proc. IEEE Int. Symp. Electromag. Compat., Atlanta, GA, 1995, pp.16-22.
  • 6
    • 33947389668 scopus 로고    scopus 로고
    • Substrate Noise Coupling in SoC Design : Modeling, Avoidance, and Validation
    • Dec
    • Afzali-Kusha. A, Nagata. M, Verghese. N.K, Allstot. D.J, "Substrate Noise Coupling in SoC Design : Modeling, Avoidance, and Validation", Proceedings of the IEEE.,Dec.2006,vol 94,pp.2109-2138
    • (2006) Proceedings of the IEEE , vol.94 , pp. 2109-2138
    • Afzali-Kusha, A.1    Nagata, M.2    Verghese, N.K.3    Allstot, D.J.4
  • 7
    • 33846097203 scopus 로고    scopus 로고
    • A Design Guide for Reducing Substrate Noise Coupling in RF Applications
    • Oct
    • A. Helmy and M. Ismail, "A Design Guide for Reducing Substrate Noise Coupling in RF Applications", IEEE Circuits and Devices Magazine, Oct.2006
    • (2006) IEEE Circuits and Devices Magazine
    • Helmy, A.1    Ismail, M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.