Interconnect and thermal-aware floorplanning for 3D microprocessors

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 98-104

  Hung, W L ^a   Link, G M ^a   Xie, Yuan ^a   Vijaykrishnan, N ^a   Irwin, M J ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D ARCHITECTURES; 90NM TECHNOLOGIES; CHIP ARCHITECTURE; FUTURE TECHNOLOGIES; INTERCONNECT POWER; MICROPROCESSOR DESIGNS; PEAK TEMPERATURES; THERMAL-AWARE FLOORPLAN;

DESIGN; MICROPROCESSOR CHIPS;

THREE DIMENSIONAL;

EID: 84886735141     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.77     Document Type: Conference Paper

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