Optimal signaling techniques for through silicon vias in 3-D integrated circuit packages

2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010

Volumn , Issue , 2010, Pages 237-240

  Grange, Matt ^a   Weerasekera, Roshan ^a   Pamunuwa, Dinesh ^a  

^a LANCASTER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; ELECTRONICS PACKAGING; ENERGY UTILIZATION; INTEGRATED CIRCUIT INTERCONNECTS; SILICON; SPICE; TIMING CIRCUITS;

3-D INTEGRATED CIRCUIT; 65 NM CMOS TECHNOLOGIES; DELAY VARIATION; ELECTRICAL MODELS; OPTIMAL SIGNALING; SIGNAL INTEGRITY; SPICE SIMULATIONS; THROUGH SILICON VIAS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 78650961498     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEPS.2010.5642598     Document Type: Conference Paper

References (14)

1. R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L-R. Zheng. Compact modelling of through-silicon vias (TSVs) in three-dimensional (3-D) integrated circuits. In Proc. IEEE Int. Conf. on 3D System Integration (3D IC), page in press, September 2009.
2. R. Weerasekera, M. Grange, D. Pamunuwa, and H. Tenhunen. On signalling over through-silicon via (tsv) interconnects in 3-d integrated circuits. In Proc. Design, Automation and Test in Europe, page in press, March 2010.
3. S.A. Kuhn, M.B. Kleiner, P. Ramm, and W. Weber. Interconnect capacitances, crosstalk, and signal delay in vertically integrated circuits. In Proc. Int. Electron Devices Meeting, pages 249-252, Dec 1995.
4. M. Grange, R. Weerasekera, D. Pamunuwa, and H. Tenhunen. Examination of delay and signal integrity metrics in through silicon vias. In Workshop Notes, Design Automation and Test in Europe Conference (DATE), 2009.
5. R. Escovar and R. Suaya. Optimal design of clock trees for multigigahertz applications. IEEE Trans. Comp.-Aided Design of Integrated Circuits and Systems, 23(3):329-345, 2004.
6. H.B. Bakoglu and J.D. Meindl. Optimal interconnection circuits for VLSI. IEEE Trans. Electron Devices, 32(5):903-909, 1985.
7. D. Pamunuwa, L.R. Zheng, and H. Tenhunen. Maximizing throughput over parallel wire structures in the deep submicrometer regime. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 11(2):224-243, 2003.
8. Rizwan Bashirullah, Wentai Liu, and Ralph K. Cavin, III. Current-mode signaling in deep submicrometer global interconnects. IEEE Trans. Very Large Scale Integrated (VLSI) Systems, 11(3):406-417, 2003.
9. A. Katoch, E. Seevinck, and H. Veendrick. Fast signal propagation for point to point on-chip long interconnects using current sensing. In Proc. European Solid-State Circuits Conf., pages 195-198, 2002.
10. R. Bashirullah, W. T. Liu, R. Cavin, and D. Edwards. A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability. IEEE Trans. Very Large Scale Integration (VLSI) Systems, 12(9):876-880, August 2004.
11. H.Zhang, V. George, and J.M. Rabaey. Low-swing on-chip signalling techniques: effectiveness and robustness. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 8(3):264-272, 2000.
12. E. Beyne and B. Swinnen. 3D system integration technologies. In IEEE Int. Conf. on Integrated Circuit Design and Tech., pages 1-3, June 2007.
13. Wei Zhao and Yu Cao. New generation of predictive technology model for sub-45nm design exploration. In Proc. Int. Symp. on Quality Electronic Design (ISQED), pages 585-590, 2006.
14. Y. Massoud, S. Majors, J. Kawa, T. Bustami, D. MacMillen, and J. White. Managing on-chip inductive effects. IEEE Trans. on Very Large Scale Integration(VLSI) Systems, 10(6):789-798, 2002.