Via first approach optimisation for through silicon via applications

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 14-19

  Laviron, Cyrille ^a   Dunne, Brendan ^b   Lapras, Valérie ^a   Galbiati, Paola ^b   Henry, David ^a   Toia, Fabrizio ^b   Moreau, Stéphane ^a   Anciant, Romain ^a   Brunet Manquat, Cahty ^a   Sillon, Nicolas ^a  

^a CEA GRENOBLE   (France)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

3D STACKING; ATTRACTIVE SOLUTIONS; BACKSIDE CONTACT; BREAKDOWN FIELD; BREAKDOWN VOLTAGE; BULK SUBSTRATES; DEEP REACTIVE ION ETCH; ELECTRICAL CHARACTERIZATION; ETCH PROFILE; HIGH TEMPERATURE; HIGH THERMAL; HIGH VOLTAGE; HIGH VOLTAGE APPLICATIONS; HIGH-VOLTAGE SEMICONDUCTORS; KELVIN STRUCTURES; METALLIZATION PROCESS; OPTIMISATIONS; PROCESS DEVELOPMENT; PROCESS STEPS; RELATIVE IMPACT; RING WIDTH; SEMICONDUCTOR PROCESS; SIDE WALLS; SILICON-ON-INSULATORS; SPECIAL STRUCTURE; SPECIFIC TEST VEHICLE; STRESS RELEASE; SURFACE FINISHING; SURFACE TOPOLOGY; THERMAL OXIDES; THROUGH-SILICON-VIA; VIA FILLING; VIA-FIRST; WEAK POINTS;

AUTOMOBILE PARTS AND EQUIPMENT; CHEMICAL MECHANICAL POLISHING; CHEMICAL POLISHING; ELECTRIC FIELDS; OPTIMIZATION; THREE DIMENSIONAL; TUNGSTEN;

SURFACES;

EID: 70349661483     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5073990     Document Type: Conference Paper

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