Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding

2010 IEEE International Interconnect Technology Conference, IITC 2010

Volumn , Issue , 2010, Pages

  Huyghebaert, Cedric ^a   Van Olmen, Jan ^a   Civale, Yann ^a   Phommahaxay, Alain ^a   Jourdain, Anne ^a   Sood, Sumant ^b   Farrens, Shari ^b   Soussan, Philippe ^a  

^a IMEC   (Belgium)

^b SUSS MicroTec Lithography GmbH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING TOOLS; CHAIN STRUCTURE; CU BONDINGS; CU INTERCONNECT; CU-INTERCONNECT TECHNOLOGY; INTERCONNECT SCHEMES; METALLIZATIONS; POLYMER BONDING; PROCESS ROUTE; SILICON WAFER-TO-WAFER BONDING; THERMO COMPRESSION BONDING; WAFER SCALE; WAFER STACKING; WAFER SURFACE;

INTERCONNECTION NETWORKS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY;

WAFER BONDING;

EID: 77955624552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2010.5510444     Document Type: Conference Paper

References (6)

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3. J. Van Olmen et al., "3D stacked IC demonstration using a through silicon via First approach," in IEEE Technical Digest of International Electron Devices Meeting, pp.1-4, 2008.
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5. J.Vaes at al., "CMP processing to enable 3D stacked IC integration" in proceedings of International Conference on Planarization/CMP Technology 2009
6. A. Jourdain et al.,Proceedings of IITC 2007, pp.207-209