Ultra low-power clocking scheme using energy recovery and clock gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 1, 2009, Pages 33-44

  Mahmoodi, Hamid ^a   Tirumalashetty, Vishy ^b   Cooke, Matthew ^c   Roy, Kaushik ^d  

^a SAN FRANCISCO STATE UNIVERSITY   (United States)

^b Itron Inc   (United States)

^c ADVANCED MICRO DEVICES   (United States)

^d Purdue University   (United States)

Author keywords

Clock gating; Energy recovery; Flip flop; Low power; Sinusoidal clock

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SYSTEM RECOVERY; ELECTRIC CLOCKS; FLIP FLOP CIRCUITS; RECOVERY;

CLOCK GATING; ENERGY RECOVERY; FLIP-FLOP; LOW POWER; SINUSOIDAL CLOCK;

CLOCKS;

EID: 58849095111     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2008453     Document Type: Article

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