-
2
-
-
64549128110
-
Floating gate super multi level NAND Flash memory technology for 30 nm and beyond
-
T. Kamigaichi Floating gate super multi level NAND Flash memory technology for 30 nm and beyond IEDM Tech Dig 2008 827 830
-
(2008)
IEDM Tech Dig
, pp. 827-830
-
-
Kamigaichi, T.1
-
3
-
-
77956545798
-
Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology
-
Y.N. Hwang Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology VLSI-TSA Tech Dig 2003 29 31
-
(2003)
VLSI-TSA Tech Dig
, pp. 29-31
-
-
Hwang, Y.N.1
-
4
-
-
0029715114
-
2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell
-
Hirano H et al. 2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell. In: Technical digest of symposium on VLSI circuits; 1996. p. 48-9.
-
(1996)
Technical Digest of Symposium on VLSI Circuits
, pp. 48-49
-
-
Hirano, H.1
-
5
-
-
0026911701
-
High speed (10-20 ns) non-volatile MRAM with folded storage elements
-
K.T.M. Ranmuthu, I.W. Ranmuthu, A.V. Pohm, C.S. Comstock, and M. Hassoun High speed (10-20 ns) non-volatile MRAM with folded storage elements IEEE Trans Magnet 28 1992 2359 2361
-
(1992)
IEEE Trans Magnet
, vol.28
, pp. 2359-2361
-
-
Ranmuthu, K.T.M.1
Ranmuthu, I.W.2
Pohm, A.V.3
Comstock, C.S.4
Hassoun, M.5
-
6
-
-
0036923301
-
Novel colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM)
-
W.W. Zhuang Novel colossal magnetoresistive thin film nonvolatile resistance random access memory (RRAM) IEDM Tech Dig 2002 193 196
-
(2002)
IEDM Tech Dig
, pp. 193-196
-
-
Zhuang, W.W.1
-
7
-
-
46849112438
-
Switching properties in spin transper torque MRAM with sub-5Onm MTJ size
-
Nam K-T et al. Switching properties in spin transper torque MRAM with sub-5Onm MTJ size. In: 7th Non-volatile memory technology symposium; 2006. p. 49-51.
-
(2006)
7th Non-volatile Memory Technology Symposium
, pp. 49-51
-
-
Nam, K.-T.1
-
8
-
-
77952126213
-
A 3bit/cell 32Gb NAND Flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s
-
Marotta GG et al. A 3bit/cell 32Gb NAND Flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s. In: Technical digest of IEEE international solid-state circuits conference; 2010. p. 444-5.
-
(2010)
Technical Digest of IEEE International Solid-state Circuits Conference
, pp. 444-445
-
-
Marotta, G.G.1
-
9
-
-
0033190134
-
Reliability of thin dielectric for nonvolatile applications
-
A. Modelli Reliability of thin dielectric for nonvolatile applications Microelectron Eng 1999 403 410
-
(1999)
Microelectron Eng
, pp. 403-410
-
-
Modelli, A.1
-
10
-
-
55549142266
-
The variable threshold transistor, a new electrically alterable, non destructive read-only-storage device
-
H. Wegener, A.J. Lincoln, H.C. Pao, M.R. O'Connell, R.E. Oleksiak, and H. Lawrence The variable threshold transistor, a new electrically alterable, non destructive read-only-storage device IEDM Tech Dig 1967 70
-
(1967)
IEDM Tech Dig
, pp. 70
-
-
Wegener, H.1
Lincoln, A.J.2
Pao, H.C.3
O'Connell, M.R.4
Oleksiak, R.E.5
Lawrence, H.6
-
11
-
-
0034315780
-
NROM: A novel localized trapping, 2-bit nonvolatile memory cell
-
B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi NROM: a novel localized trapping, 2-bit nonvolatile memory cell IEEE Electron Dev Lett 21 2000 543 545
-
(2000)
IEEE Electron Dev Lett
, vol.21
, pp. 543-545
-
-
Eitan, B.1
Pavan, P.2
Bloom, I.3
Aloni, E.4
Frommer, A.5
Finzi, D.6
-
12
-
-
5444274648
-
Statistical simulations for Flash memory reliability analysis and prediction
-
L. Larcher, and P. Pavan Statistical simulations for Flash memory reliability analysis and prediction IEEE Trans Electron Dev 24 2004 1636 1643
-
(2004)
IEEE Trans Electron Dev
, vol.24
, pp. 1636-1643
-
-
Larcher, L.1
Pavan, P.2
-
18
-
-
36148939193
-
Metal-oxide-high-κ dielectric-oxide-semiconductor (MOHOS) capacitors and field-effect transistors for memory applications
-
H.-H. Hsu, I.Y. Chang, and J.Y. Lee Metal-oxide-high-κ dielectric-oxide-semiconductor (MOHOS) capacitors and field-effect transistors for memory applications IEEE Electron Dev Lett 28 2007 964 966
-
(2007)
IEEE Electron Dev Lett
, vol.28
, pp. 964-966
-
-
Hsu, H.-H.1
Chang, I.Y.2
Lee, J.Y.3
-
19
-
-
67650423946
-
Charge-trapping-type Flash memory device with stacked high-κ charge-trapping layer
-
P.-H. Tsai, K.-S. Chang-Liao, T.-C. Liu, T.-K. Wang, P.-J. Tzeng, and C.-H. Lin Charge-trapping-type Flash memory device with stacked high-κ charge-trapping layer IEEE Electron Dev Lett 30 2009 775 777
-
(2009)
IEEE Electron Dev Lett
, vol.30
, pp. 775-777
-
-
Tsai, P.-H.1
Chang-Liao, K.-S.2
Liu, T.-C.3
Wang, T.-K.4
Tzeng, P.-J.5
Lin, C.-H.6
-
21
-
-
31044455312
-
High dielectric constant gate oxides for metal oxide Si transistors
-
J. Robertson High dielectric constant gate oxides for metal oxide Si transistors Rep Prog Phys 69 2006 327 396
-
(2006)
Rep Prog Phys
, vol.69
, pp. 327-396
-
-
Robertson, J.1
-
22
-
-
59649100655
-
Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation
-
C. Sandhya, U. Ganguly, N. Chattar, C. Olsen, S.M. Seutter, and L. Date Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation IEEE Electron Dev Lett 30 2009 171 173
-
(2009)
IEEE Electron Dev Lett
, vol.30
, pp. 171-173
-
-
Sandhya, C.1
Ganguly, U.2
Chattar, N.3
Olsen, C.4
Seutter, S.M.5
Date, L.6
-
23
-
-
62549154474
-
Erase and retention improvements in charge trap flash through engineered charge storage layer
-
N. Goel, D.C. Gilmer, H. Park, V. Diaz, Y. Sun, and J. Price Erase and retention improvements in charge trap flash through engineered charge storage layer IEEE Electron Dev Lett 30 2009 216 218
-
(2009)
IEEE Electron Dev Lett
, vol.30
, pp. 216-218
-
-
Goel, N.1
Gilmer, D.C.2
Park, H.3
Diaz, V.4
Sun, Y.5
Price, J.6
-
24
-
-
0021374999
-
Gap states in silicon nitride
-
J. Robertson, and M.J. Powel Gap states in silicon nitride Appl Phys Lett 44 1984 415 417
-
(1984)
Appl Phys Lett
, vol.44
, pp. 415-417
-
-
Robertson, J.1
Powel, M.J.2
-
25
-
-
1642587312
-
Lateral charge transport in the nitride layer of the NROM non-volatile memory device
-
A. Shappir, Y. Shacham-Diamand, E. Lusky, I. Bloom, and B. Eitan Lateral charge transport in the nitride layer of the NROM non-volatile memory device Microelectron Eng 72 2004 426 433
-
(2004)
Microelectron Eng
, vol.72
, pp. 426-433
-
-
Shappir, A.1
Shacham-Diamand, Y.2
Lusky, E.3
Bloom, I.4
Eitan, B.5
-
26
-
-
37749038893
-
Hole distributions in NROM devices: Profiling method and effects on reliability
-
A. Padovani, L. Larcher, and P. Pavan Hole distributions in NROM devices: profiling method and effects on reliability IEEE Trans Electron Dev 55 2008 343 349
-
(2008)
IEEE Trans Electron Dev
, vol.55
, pp. 343-349
-
-
Padovani, A.1
Larcher, L.2
Pavan, P.3
-
27
-
-
11144234851
-
The two-bit NROM reliability
-
A. Shappir, E. Lusky, G. Cohen, I. Bloom, M. Janai, and B. Eitan The two-bit NROM reliability IEEE Trans Dev Mater Rel 4 2004 397 403
-
(2004)
IEEE Trans Dev Mater Rel
, vol.4
, pp. 397-403
-
-
Shappir, A.1
Lusky, E.2
Cohen, G.3
Bloom, I.4
Janai, M.5
Eitan, B.6
-
28
-
-
11144229439
-
Data retention reliability model of NROM nonvolatile memory products
-
M. Janai, B. Eitan, A. Shappir, E. Lusky, I. Bloom, and G. Cohen Data retention reliability model of NROM nonvolatile memory products IEEE Trans Dev Mater Rel 4 2004 404 415
-
(2004)
IEEE Trans Dev Mater Rel
, vol.4
, pp. 404-415
-
-
Janai, M.1
Eitan, B.2
Shappir, A.3
Lusky, E.4
Bloom, I.5
Cohen, G.6
-
29
-
-
34548754508
-
Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash memory
-
Kang C et al. Effects of lateral charge spreading on the reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash memory. In: Proceedings of IEEE international reliability physics symposium; 2007. p. 167-70.
-
(2007)
Proceedings of IEEE International Reliability Physics Symposium
, pp. 167-170
-
-
Kang, C.1
-
30
-
-
0038720813
-
Data retention behavior of a SONOS type two-bit storage Flash memory cell
-
W.J. Tsai Data retention behavior of a SONOS type two-bit storage Flash memory cell IEDM Tech Dig 2001 32.6.1 32.6.4
-
(2001)
IEDM Tech Dig
, pp. 3261-3264
-
-
Tsai, W.J.1
-
31
-
-
77956169854
-
Role and compensation of holes and electrons under erase of TANOS memories: Evidences of dipole formation and its impact on reliability
-
Vandelli L et al. Role and compensation of holes and electrons under erase of TANOS memories: evidences of dipole formation and its impact on reliability. In: Proceedings of international reliability physics symposium, vol. 1. 2010. p. 731-7.
-
(2010)
Proceedings of International Reliability Physics Symposium
, vol.1
, pp. 731-737
-
-
Vandelli, L.1
-
32
-
-
0000090297
-
Layered tunnel barriers for nonvolatile memory devices
-
K.K. Likharev Layered tunnel barriers for nonvolatile memory devices Appl Phys Lett 73 1998 2137 2139
-
(1998)
Appl Phys Lett
, vol.73
, pp. 2137-2139
-
-
Likharev, K.K.1
-
33
-
-
0038732556
-
VARIOT: A multilayer tunnel barrier concept for low-voltage nonvolatile memory devices
-
B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. De Meyer VARIOT: a multilayer tunnel barrier concept for low-voltage nonvolatile memory devices IEEE Electron Dev Lett 24 2003 99 101
-
(2003)
IEEE Electron Dev Lett
, vol.24
, pp. 99-101
-
-
Govoreanu, B.1
Blomme, P.2
Rosmeulen, M.3
Van Houdt, J.4
De Meyer, K.5
-
34
-
-
40749158789
-
Operational voltage reduction of Flash memory using high-κ composite tunnel barriers
-
S. Verma, E. Pop, P. Kapur, K. Parat, and K.C. Saraswat Operational voltage reduction of Flash memory using high-κ composite tunnel barriers IEEE Electron Dev Lett 29 2008 252 254
-
(2008)
IEEE Electron Dev Lett
, vol.29
, pp. 252-254
-
-
Verma, S.1
Pop, E.2
Kapur, P.3
Parat, K.4
Saraswat, K.C.5
-
35
-
-
0036639637
-
Material issues for layered tunnel barrier structures
-
J.D. Casperson, L.D. Bell, and H.A. Atwater Material issues for layered tunnel barrier structures J Appl Phys 92 2002 261 267
-
(2002)
J Appl Phys
, vol.92
, pp. 261-267
-
-
Casperson, J.D.1
Bell, L.D.2
Atwater, H.A.3
-
36
-
-
28344451914
-
4 multilayer for Flash memory application
-
4 multilayer for Flash memory application Appl Phys Lett 87 2005 152106
-
(2005)
Appl Phys Lett
, vol.87
, pp. 152106
-
-
Hong, S.H.1
-
37
-
-
2942674774
-
Engineering on tunnel barrier and dot surface in Si nanocrystal memories
-
S.J. Baik, S. Choi, U-In Chung, and J.T. Moon Engineering on tunnel barrier and dot surface in Si nanocrystal memories Solid-State Electron 48 2004 1475 1481
-
(2004)
Solid-State Electron
, vol.48
, pp. 1475-1481
-
-
Baik, S.J.1
Choi, S.2
U-In, C.3
Moon, J.T.4
-
38
-
-
36148963642
-
High-quality high-κ HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories
-
Y. Liu High-quality high-κ HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories Microelectron Eng 85 2008 45 48
-
(2008)
Microelectron Eng
, vol.85
, pp. 45-48
-
-
Liu, Y.1
-
39
-
-
33748108365
-
Electron trap generation in high-k gate stacks by constant voltage stress
-
DOI 10.1109/TDMR.2006.877865, 1673699
-
C.D. Young, D. Heh, S.V. Nadkarni, R. Choi, J.J. Peterson, and J. Barnett Electron trap generation in high-k gate stacks by constant voltage stress IEEE Trans Dev Mater Rel 6 2006 123 131 (Pubitemid 44304117)
-
(2006)
IEEE Transactions on Device and Materials Reliability
, vol.6
, Issue.2
, pp. 123-131
-
-
Young, C.D.1
Heh, D.2
Nadkarni, S.V.3
Choi, R.4
Peterson, J.J.5
Barnett, J.6
Lee, B.H.7
Bersuker, G.8
-
40
-
-
28044459163
-
2 gate stacks for application to non-volatile memory devices
-
2 gate stacks for application to non-volatile memory devices Solid-State Electron 49 2005 1833 1840
-
(2005)
Solid-State Electron
, vol.49
, pp. 1833-1840
-
-
Buckley, J.1
-
41
-
-
0038009946
-
Enhanced tunneling current effect for nonvolatile memory applications
-
B. Govoreanu, P. Blomme, J. Van Houdt, and K. De Meyer Enhanced tunneling current effect for nonvolatile memory applications Jpn J Appl Phys 42 2003 2020 2024
-
(2003)
Jpn J Appl Phys
, vol.42
, pp. 2020-2024
-
-
Govoreanu, B.1
Blomme, P.2
Van Houdt, J.3
De Meyer, K.4
-
45
-
-
33747831053
-
2 tunnel barrie
-
2 tunnel barrie Appl Phys Lett 89 2006 083109
-
(2006)
Appl Phys Lett
, vol.89
, pp. 083109
-
-
Seol, K.S.1
-
46
-
-
33847734692
-
BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability
-
H.T. Lue BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability IEDM Tech Dig 2005 547 550
-
(2005)
IEDM Tech Dig
, pp. 547-550
-
-
Lue, H.T.1
-
47
-
-
77950148571
-
Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100 K cycle endurance
-
D.C. Gilmer Band engineered tunnel oxides for improved TANOS-type flash program/erase with good retention and 100 K cycle endurance VLSI-TSA Tech Dig 2009 156 157
-
(2009)
VLSI-TSA Tech Dig
, pp. 156-157
-
-
Gilmer, D.C.1
-
54
-
-
49049102369
-
3 tunnel dielectric for future Flash memories generations
-
3 tunnel dielectric for future Flash memories generations Ultimate Integration Silicon 2008 111 114
-
(2008)
Ultimate Integration Silicon
, pp. 111-114
-
-
Padovani, A.1
-
55
-
-
0043175221
-
Statistical simulation of leakage currents in MOS and Flash memory devices with a new multiphonon trap-assisted tunneling model
-
L. Larcher Statistical simulation of leakage currents in MOS and Flash memory devices with a new multiphonon trap-assisted tunneling model IEEE Trans Electron Dev 50 2003 1246 1253
-
(2003)
IEEE Trans Electron Dev
, vol.50
, pp. 1246-1253
-
-
Larcher, L.1
-
56
-
-
70449115477
-
Understanding barrier engineered charge-trapping NAND Flash devices with and without high-κ dielectric
-
Lue HT et al. Understanding barrier engineered charge-trapping NAND Flash devices with and without high-κ dielectric. In: Proceedings of IEEE international reliability physics symposium; 2009. p. 877-82.
-
(2009)
Proceedings of IEEE International Reliability Physics Symposium
, pp. 877-882
-
-
Lue, H.T.1
-
57
-
-
70449094578
-
Study of the charge-trapping characteristics of silicon-rich nitride thin films using the gate-sensing and channel-sensing (GSCS) method
-
Lu CP et al. Study of the charge-trapping characteristics of silicon-rich nitride thin films using the gate-sensing and channel-sensing (GSCS) method. In: Proceedings of IEEE international reliability physics symposium; 2009. p. 883-6.
-
(2009)
Proceedings of IEEE International Reliability Physics Symposium
, pp. 883-886
-
-
Lu, C.P.1
-
59
-
-
67349235658
-
Reliability of charge trapping memories with high-κ control dielectric
-
G. Molas Reliability of charge trapping memories with high-κ control dielectric Microelectronic Eng 86 2009 1796 1803
-
(2009)
Microelectronic Eng
, vol.86
, pp. 1796-1803
-
-
Molas, G.1
-
61
-
-
70350721642
-
Performance improvement in charge-trap Flash memory using Lanthanum-based high-κ blocking oxide
-
W. He, J. Pu, D.S.H. Chan, and B.J. Cho Performance improvement in charge-trap Flash memory using Lanthanum-based high-κ blocking oxide IEEE Trans Electron Dev 56 2009 2746 2751
-
(2009)
IEEE Trans Electron Dev
, vol.56
, pp. 2746-2751
-
-
He, W.1
Pu, J.2
Chan, D.S.H.3
Cho, B.J.4
-
62
-
-
67349176413
-
Data retention characteristics of MANOS-type Flash memory device with different metal gates at various levels of charge injection
-
M. Chan Data retention characteristics of MANOS-type Flash memory device with different metal gates at various levels of charge injection Microelectronics Eng 86 2009 1804 1806
-
(2009)
Microelectronics Eng
, vol.86
, pp. 1804-1806
-
-
Chan, M.1
-
63
-
-
68249146434
-
Modeling TANOS memory program transients to investigate charge trapping dynamics
-
A. Padovani, L. Larcher, D. Heh, and G. Bersuker Modeling TANOS memory program transients to investigate charge trapping dynamics IEEE Electron Dev Lett 30 2009 882 884
-
(2009)
IEEE Electron Dev Lett
, vol.30
, pp. 882-884
-
-
Padovani, A.1
Larcher, L.2
Heh, D.3
Bersuker, G.4
-
64
-
-
50249096298
-
Improvement of TANOS NAND Flash performance by the optimization of a sealing layer
-
Breuil L, Furnémont A, Rothschild A, Van den Bosch G, Cacciato A, Van Houdt J. Improvement of TANOS NAND Flash performance by the optimization of a sealing layer. In: Proceedings of non-volatile semiconductor memory workshop; 2008. p. 126-7.
-
(2008)
Proceedings of Non-volatile Semiconductor Memory Workshop
, pp. 126-127
-
-
Breuil, L.1
Furnémont, A.2
Rothschild, A.3
Den Bosch, G.4
Cacciato, A.5
Houdt, J.6
-
65
-
-
67349137949
-
3 bi-layer blocking oxide in nitride-trap non-volatile memories
-
3 bi-layer blocking oxide in nitride-trap non-volatile memories Solid-State Electron 53 2009 786 791
-
(2009)
Solid-State Electron
, vol.53
, pp. 786-791
-
-
Bocquet, M.1
-
66
-
-
77957908492
-
Charge loss in TANOS devices caused by Vt sensing measurements during retention
-
Park H, Bersuker G, Gilmer D, Lim KY, Jo M, Hwang H, et al. Charge loss in TANOS devices caused by Vt sensing measurements during retention. In: Proceedings of IEEE international memory workshop; 2010. p. 175-6.
-
(2010)
Proceedings of IEEE International Memory Workshop
, pp. 175-176
-
-
Park, H.1
Bersuker, G.2
Gilmer, D.3
Lim, K.Y.4
Jo, M.5
Hwang, H.6
-
67
-
-
0042172980
-
3 gate stacks with TiN electrodes
-
3 gate stacks with TiN electrodes IEEE Trans Electron Dev 50 2003 1261 1268
-
(2003)
IEEE Trans Electron Dev
, vol.50
, pp. 1261-1268
-
-
Kerber, A.1
|