Monte-Carlo simulations of flash memory array retention

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Padovani, A ^a   Larcher, L ^b   Chimenton, A ^a   Pavan, P ^b  

^a UNIVERSITY OF FERRARA   (Italy)

^b UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA REDUCTION; MONTE CARLO METHODS; RELIABILITY ANALYSIS;

FLASH TECHNOLOGY DEVELOPMENT; MONTE CARLO SIMULATORS; VOLTAGE ACCELERATED STRESSES;

FLASH MEMORY;

EID: 34548828247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378963     Document Type: Conference Paper

References (12)

1. R. Moazzami et al., IEDM Tech. Dig., 1992, pp.139-142.
2. S. Takagi et al., IEEE Trans. Electron Devices, Vol. 46,(2), pp.348-354, 1999.
3. M. Hermann et al., J. Appl. Phys., Vol. 77(9), pp.4522-4540, 1995.
4. th IEEE-IRPS, Dallas (USA), pp.7-20, 2002.
5. R. Degraeve et al., IEEE Trans. on Electron Device, Vol. 51(9), pp.1392-1400, 2004.
6. D. Ielmini et al., IEEE Trans. on Device and Materials Reliability, Vol. 4(3), pp.320-326, 2004.
7. D. Ielmini et al., IEEE Electron Devices Letters, Vol. 23(1), pp. 40-42, 2002.
8. th IEEE-IRPS, Phoenix (USA), 2007.
9. G. Cellere et al., IEEE Trans. on Nuclear, Science, Vol. 52(6), pp.2144-2152, 2005.
10. L. Larcher, IEEE Trans. on Electron Device, Vol. 50(5), pp.1246-1253, 2003.
11. P. Pavan et al., Proc. of the IEEE, Vol. 85 (8), pp.1248-1271, 1997.
12. P. Pellati et al., IEEE Trans. Instrum. Meas., Vol. 50, pp. 1162-1166, 2001.