Engineering on tunnel barrier and dot surface in Si nanocrystal memories

Solid-State Electronics

Volumn 48, Issue 9, 2004, Pages 1475-1481

  Baik, Seung Jae ^a   Choi, Siyoung ^a   Chung, U In ^a   Moon, Joo Tae ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ANALYSIS; DATA STORAGE EQUIPMENT; DIELECTRIC MATERIALS; GATES (TRANSISTOR); INTERFACES (MATERIALS); MATHEMATICAL MODELS; PROBLEM SOLVING; RELIABILITY; SELF ASSEMBLY; SILICON; THERMOANALYSIS; VOLTAGE CONTROL;

NAND GATES; NONVOLATILE MEMORIES; SILICON NANOCRYSTALLINE MEMORIES; TUNNEL BARRIERS;

NANOSTRUCTURED MATERIALS;

EID: 2942674774     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.03.011     Document Type: Conference Paper

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