Electrical characteristics of memory devices with a high-k HfO2 trapping layer and dual SiO2/Si3 N4 tunneling layer

IEEE Transactions on Electron Devices

Volumn 54, Issue 10, 2007, Pages 2699-2705

  Wang, Ying Qian ^a,b   Hwang, Wam Sik ^a   Zhang, Gang ^c   Samudra, Ganesh ^a   Yeo, Yee Chia ^a   Yoo, Won Jong ^c  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^c Sungkyunkwan University   (South Korea)

Author keywords

Dual tunneling layer (DTL); Endurance; High k trapping layer; Program erase speed; Retention

Indexed keywords

CHARGE INJECTION; COMPUTER PROGRAMMING; ELECTRIC PROPERTIES; FLASH MEMORY;

DUAL TUNNELING LAYER; HIGH-K MATERIALS; PROGRAM/ERASE SPEED;

DATA STORAGE EQUIPMENT;

EID: 35148842428     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.904396     Document Type: Article

References (19)

1. "Front end processes," International Technology Roadmap for Semiconductors (ITRS), pp. 51-52, 2005.
2. 3 with TaN metal gate for multi-giga bit flash memories," in IEDM Tech. Dig., 2003, pp. 26.5.1-26.5.4.
3. 3-TaN) structure compatible to conventional NAND Flash memory," in Proc. IEEE NVSMW, 2006, pp. 54-55.
4. th and good retention," in VLSI Symp. Tech. Dig., 2005, pp. 210-211.
5. 2/HfA1O/HfSiO/HfA1O gate stack for memory application," in IEDM Tech. Dig., 2005, pp. 169-172.
6. 3 for high-density Flash memory," Appl. Phys. Lett., vol. 86, no. 15, pp. 152908 1-152908 3, Apr. 2005.
7. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-k gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, May 2001.
8. Y. N. Tan, W. K. Chim, B. J. Cho, and W. K. Choi, "Over-erase phenomenon in SONOS-type Hash memory and its minimization using a hafnium oxide charge storage layer," IEEE Trans. Electron Devices vol. 51, no. 7, pp. 1143-1147, Jul. 2004.
9. M. She, "Semiconductor flash memory scaling," Ph.D. dissertation, U.C. Berkeley, Berkeley, CA, 2003.
10. H. T. Lue, S.-Y. Wang, E.-K. Lai, Y.-H. Shih, S.-C. Lai, L.-W. Yang, K.-C. Chen, J. Ku, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, "BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability," in IEDM Tech. Dig., 2005, pp. 555-558.
11. K. K. Likharev, "Layered tunnel barriers for nonvolatile memory devices," Appl. Phys. Lett., vol. 73, no. 15, pp. 2137-2139, Oct. 1998.
12. S. J. Baik, S. Choi, U.-I. Chung, and J. T. Moon, "High speed and nonvolatile Si nanocrystal memory for scaled Flash technology using highly field-sensitive tunnel barrier," in IEDM Tech. Dig., 2003, pp. 22.3.1-22.3.4.
13. 4 multilayer for Flash memory application," Appl. Phys. Lett., vol. 87, no. 15, pp. 152 106 1-152 106 3, Oct. 2005.
14. B. Govoreanu, P. Blomme, M. Rosmeulen, J. Van Houdt, and K. D. Meyer, "VARIOT: A novel multilayer tunnel barrier concept for low-voltage nonvolatile memory devices," IEEE Electron Device Lett., vol. 24, no. 2, pp. 99-101, Feb. 2003.
15. B. Govoreanu, P. Blomme, J. V. Houdt, and K. D. Meyer, "Enhanced tunneling current effect for nonvolatile memory applications," Jpn. J. Appl. Phys., vol. 42, no. 4B, pp. 2020-2024, Apr. 2003.
16. H. Bachhofer, H. Reisinger, H. Bertagnolli, and H. von Philipsborn, "Transient conduction in multidielectric silicon-oxide-nitride-oxide semiconductor structures," J. Appl. Phys., vol. 89, no. 5, pp. 2791-2800, Mar. 2001.
17. Y. Yang and M. H. White, "Charge retention of scaled SONOS nonvolatile memory devices at elevated temperatures," Solid State Electron., vol. 44, no. 6, pp. 949-958, Jun. 2000.
18. K.-H. Wu, H.-C. Chien, C.-C. Chan, T.-S. Chen, and C.-H. Kao, "SONOS device with tapered bandgap nitride layer," IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 987-992, May 2005.
19. Y.-B. Park and D. K. Schroder, "Degradation of thin tunnel gate oxide under Constant Fowler-Nordheim current stress for a Hash EEPROM," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1361-1368, Jun. 1998.