Effect of SiN on performance and reliability of charge trap flash (CTF) under Fowler-Nordheim tunneling program/erase operation

IEEE Electron Device Letters

Volumn 30, Issue 2, 2009, Pages 171-173

  Sandhya, C ^a   Ganguly, Undayan ^b   Chattar, Nihit ^a   Olsen, Christopher ^b   Seutter, Sean M ^b   Date, Lucien ^b   Hung, Raymond ^b   Vasi, Juzer M ^a   Mahapatra, Souvik ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b APPLIED MATERIALS INC   (United States)

Author keywords

Charge trap flash (CTF); Cycling endurance; Program erase (P E) window; Retention; SANOS; Silicon nitride (SiN); SONOS

Indexed keywords

CHARGE TRAPPING; DURABILITY; ELECTRON TUBE DIODES; NITRIDES; RELIABILITY; SILICON NITRIDE; STOICHIOMETRY; WINDOWS;

CHARGE TRAP FLASH (CTF); CYCLING ENDURANCE; PROGRAM/ERASE (P/E) WINDOW; RETENTION; SANOS; SILICON NITRIDE (SIN); SONOS;

FLASH MEMORY;

EID: 59649100655     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2008.2009552     Document Type: Article

References (13)

1. K. Kim, "Technology for sub-50 nm DRAM and NAND Flash manufacturing," in IEDM Tech. Dig., 2005, pp. 333-336.
2. C. Sandhya, U. Ganguly, K. K. Singh, P. K. Singh, C. Olsen, S. Seutter, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, "Nitride engineering and the effect of interfaces on Charge Trap Flash performance and reliability," in Proc. Int. Reliab. Phys. Symp., 2008, pp. 406-412.
3. C. Sandhya, U. Ganguly, K. K. Singh, C. Olsen, S. Seutter, G. Conti, K. Ahmed, N. Krishna, J. Vasi, and S. Mahapatra, "The effect of band gap engineering of the nitride storage node on performance and reliability of Charge Trap Flash," in Proc. Int. Symp. Phys. Fail. Anal. Integr. Circuits, 2008, pp. 224-230.
4. H. C. Chien, C. H. Kao, W. Chang, and T. K. Tsai, "Two-bit SONOS type Flash using a band engineering in the nitride layer," Microelectron. Eng., vol. 80, no. 1, pp. 256-260, Jun. 2005.
5. Z. L. Huo, J. Yang, S. Lim, S. Baik, J. Lee, J. H. Han, I. Yeo, U. Chung, J. T. Moon, and B. Ryu, "Band engineered charge trap layer for highly reliable MLC Flash memory," in VLSI Symp. Tech. Dig., 2007, pp. 138-139.
6. D. Kwak, J. Park, K. Kim, Y. Yim, S. Ahn, Y. Park, J. Kim, W. Jeong, J. Kim, M. Park, B. Yoo, S. Song, H. Kim, J. Sim, S. Kwon, B. Hwang, H. Park, S. Kim, Y. Lee, H. Shin, N. Yim, K. Lee, M. Kim, Y. Lee, J. Park, S. Park, J. Jung, and K. Kim, "Integration technology of 30 nm generation multi-level NAND Flash for 64 Gb NAND Flash memory," in VLSI Symp. Tech. Dig., 2007, pp. 12-13.
7. S. Y. Wang, H. T. Lue, E. K. Lai, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, "Reliability and processing effects of band-gap engineered SONOS (BE-SONOS) Flash memory," in Proc. Int. Reliab. Phys. Symp., 2007, pp. 171-176.
8. J. Robertson and M. J. Powell, "Gap states in silicon nitride," Appl. Phys. Lett., vol. 44, no. 4, pp. 415-417, Feb. 1984.
9. M. Peterson and Y. Roizin, "Density functional theory study of deep traps in silicon nitride memories," Appl. Phys. Lett., vol. 89, no. 5, pp. 053 511-1-053 511-3, Aug. 2006.
10. S. M. Sze, "Dielectric and polysilicon deposition, principles of chemical vapor deposition," in VLSI Technology, 2nd ed. New York: McGraw-Hill, 1988, ch. 6, p. 261.
11. T. H. Kim, I. H. Park, J. D. Lee, H. C. Shin, and B. G. Park, "Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures," App. Phys. Lett., vol. 89, no. 6, pp. 63 508-1-63 508-3, Aug. 2006.
12. S. J. Wrazien, Y. Zhao, J. D. Krayer, and M. H. White, "Characterization of SONOS oxynitride nonvolatile semiconductor memory devices," Solid State Electron., vol. 47, no. 5, pp. 885-891, May 2003.
13. A. Paul, C. Sridhar, S. Gedam, and S. Mahapatra, "Comprehensive simulation of program, erase and retention in charge trapping Flash memories," in IEDM Tech. Dig., 2006, pp. 393-396.