Multi-Layer High-K Tunnel Barrier for a Voltage Scaled NAND-Type Flash Cell

2009 IEEE Workshop on Microelectronics and Electron Devices, WMED 2009

Volumn , Issue , 2009, Pages 49-51

  Ramaswamy, Nirmal ^a   Yeh, Chun Chen ^b   Krishnamohan, Tejas ^c   Gowda, Srivardhan ^c   Rocklein, Noel ^a   Brewer, Rhett ^c   Graettinger, Thomas ^a   Min, Kyu ^c  

^a MICRON TECHNOLOGY INC   (United States)

^b YALE UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

High K dielectric; Low voltage programming erasing; NAND Flash cell; Tunnel oxide

Indexed keywords

CHARGE LOSS; FLASH CELL; HIGH-K DIELECTRIC; LOW VOLTAGE PROGRAMMING/ERASING; LOW VOLTAGES; LOW-K MATERIALS; LOW-VOLTAGE; METAL INSULATORS; NAND FLASH; NAND FLASH CELL; PROGRAM/ERASE; TIN GATES; TUNNEL BARRIER; TUNNEL OXIDE; TUNNEL OXIDES;

CELL MEMBRANES; ELECTRIC POTENTIAL; ELECTRON DEVICES; METAL INSULATOR BOUNDARIES; MICROELECTRONICS; NITRIDES; SILICON OXIDES; TIN OXIDES; TITANIUM NITRIDE; WINDOWS;

WIND TUNNELS;

EID: 67650104764     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WMED.2009.4816146     Document Type: Conference Paper

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