Operational voltage reduction of flash memory using high-κ composite tunnel barriers

IEEE Electron Device Letters

Volumn 29, Issue 3, 2008, Pages 252-254

  Verma, Sarves ^a   Pop, Eric ^b,c   Kapur, Pawan ^a   Parat, Krishna ^b   Saraswat, Krishna C ^a  

^a Stanford University   (United States)

^b INTEL CORPORATION   (United States)

^c University of Illinois at Urbana Champaign   (United States)

Author keywords

Flash memory; Flash operating constraints; High dielectrics; Program disturb; Read disturb; Retention; Tunnel barrier engineering

Indexed keywords

DIELECTRIC MATERIALS; VOLTAGE CONTROL;

FLASH OPERATING CONSTRAINTS; PROGRAM DISTURB; READ DISTURB; TUNNEL BARRIER ENGINEERING;

FLASH MEMORY;

EID: 40749158789     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.915376     Document Type: Article

References (8)

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