On the physical mechanism of the NROM memory erase

IEEE Transactions on Electron Devices

Volumn 51, Issue 10, 2004, Pages 1593-1599

  Larcher, Luca ^a   Pavan, Paolo ^a   Eitan, Boaz ^b  

^a UNIVERSITY OF MODENA AND REGGIO EMILIA   (Italy)

^b Saifun Semiconductors Ltd   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRON EMISSION; ELECTRON TRAPS; ELECTRON TUNNELING; FLASH MEMORY; HOLE TRAPS; MATHEMATICAL MODELS; RELIABILITY THEORY; ROM;

DEVICE SIMULATIONS; HOT HOLE INJECTION; SEMICONDUCTOR DEVICE RELIABILITY; SEMICONDUCTOR MEMORIES;

MOSFET DEVICES;

EID: 5444262659     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.834897     Document Type: Article

References (24)

1. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "Can NROM, a 2-bit trapping storage cell, give a real challenge to floating gate cells?," in Proc. SSDM, Tokyo, Japan, Sept. 1999, pp. 522-524.
2. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, pp. 543-545, Nov. 2000.
3. E. Lusky, Y. Shacham-Diamand, B. Eitan, and I. Bloom, "Characterization of channel hot electron injection by the subthreshold slope of NROM device," IEEE Electron Device Lett., vol. 22, pp. 556-557, Nov. 2001.
4. L. Larcher, Pavan, G. Verzellesi, E. Lusky, I. Bloom, and B. Eitan, "Impact of programming charge distribution on threshold voltage and subthreshold slope of NROM memory cells," IEEE Trans. Electron Devices, vol. 49, pp. 193-194, Nov. 2002.
5. W. J. Tsai, S. H. Gu, N. K. Zous, C. C. Yeh, C. C. Liu, C. H. Chen, W. Tahui, S. Pan, and C.-Y. Lu, "Cause of data retention loss in a nitride-based localized trapping storage flash memory," in Proc. IRPS, Dallas, TX, 2002, pp. 34-38.
6. M. Janai, "Data retention, endurance, and acceleration factors of NROM devices," in Proc. IRPS, Dallas, TX, 2003, pp. 502-505.
7. I. Fujiwara, H. Aozasa, K. Nomoto, S. Tanaka, and T. Kobayashi, "High speed program/erase sub 100 nm MONOS memory cell," in Proc. Non-Volatile Semiconductor Memory Workshop, Monteray, CA, 2001, pp. 75-77.
8. C. T. Swift, G. L. Chindalore, K. Harber, T. S. Harp, A. Hoefler, C. M. Hong, P. A. Ingersoll, C. B. Li, E. J. Prinz, and J. A. Yater, "An embedded 90 nm SONOS Non-volatile memory utilizing hot electron programming and uniform tunnel erase," in IEDM Tech. Dig., 2002, pp. 927-930.
9. M. Tanaka, S. Saida, Y. Mitani, I. Mizushima, and Y. Tsunashima, "Highly reliable MONOS devices with optimized silicon nitride film having deuterium terminated charge traps," in IEDM Tech. Dig., 2002, pp. 237-240.
10. M. K. Cho and D. M. Kim, "Simultaneous hot-hole injection at drain and source for efficient erase and excellent endurance in SONOS flash EPROM cells," IEEE Electron Device Lett., vol. 24, pp. 260-262, Apr. 2003.
11. G. Ingrosso, L. Selmi, and E. Sangiorgi, "Monte Carlo simulation of program and erase charge distributions in NROM devices," in Proc. ESSDERC, Bologna, Italy, 2002.
12. R. Bez, D. Cantarelli, and P. Cappelletti, "Experimental transient analysis of the tunnel current in EEPROM cells," IEEE Trans. Electron Devices, vol. 37, pp. 1081-1086, Apr. 1990.
13. A. Schenk, "Rigorous theory and simplified model of the band-to-band tunnelling in silicon," Solid State Electron., vol. 36, no. 1, pp. 19-34, 1993.
14. 4: Experiment and numerical simulation," Appl. Surf. Sci., vol. 113/114, pp. 417-421, 1997.
15. 4 in oxide/nitride/oxide for metal/oxide/nitride/oxide/silicon nonvolatile memory," J. Appl. Phys., vol. 38, pp. 1441-1447, 1999.
16. Z. A. Weinberg, "On tunneling in metal-oxide-silicon structure," J. Appl. Phys., vol. 53, no. 7, pp. 5052-5056, 1982.
17. + poly-gate PMOSFETs with ultrathin gate oxides," IEEE Trans. Electron Devices, vol. 47, pp. 2161-2166, Nov. 2000.
18. W.-C. Lee and C. Hu, "Modeling CMOS tunneling currents through ultra-thin gate oxide due to conduction- and valence-band electron and hole tunneling," IEEE Trans. Electron Devices, vol. 48, pp. 1366-1373, July 2001.
19. C. Hu, "Lucky-electron model of channel hot electron emission," in IEDM Tech. Dig., 1979, pp. 223-226.
20. P. Cappelletti, C. Golla, P. Olivo, and E. Zanoni, Flash Memories. New York:. Kluwer, 1999.
21. B. Eitan and D. Frohman-Bentchkowsky, "Hot-electron injection into the oxide in n-channel MOS devices," IEEE Trans. Electron Devices, vol. 28, pp. 328-340, Mar. 1981.
22. D. Cassi and B. Riccò, "An analytical model of the energy distribution of hot electrons," IEEE Trans. Electron Devices, vol. 37, pp. 1514-1521, June 1990.
23. C. Fiegna, F. Venturi, M. Melanotte, E. Sangiorgi, and B. Riccò, "Simple and efficient modeling of EPROM writing," IEEE Trans. Electron Devices, vol. 38, pp. 603-610, Mar. 1991.
24. K. Hasnat, C.-F. Yeap, S. Jallepalli, S. A. Hareland, W.-K. Shih, V. M. Agostinelli, A. F. Tasch, and C. M. Maziar, "Thermoionic emission model of electron gate current in submicron nMOSFET's," IEEE Trans. Electron Devices, vol. 44, pp. 129-138, Jan. 1997.