Erase and retention improvements in charge trap flash through engineered charge storage layer

IEEE Electron Device Letters

Volumn 30, Issue 3, 2009, Pages 216-218

  Goel, Niti ^a   Gilmer, D C ^b   Park, H ^b   Diaz, V ^b   Sun, Y ^c   Price, J ^b   Park, C ^b   Pianetta, P ^c   Kirsch, P D ^b   Jammy, R ^b  

^a INTEL CORPORATION   (United States)

^b SEMATECH   (United States)

^c SLAC NATIONAL ACCELERATOR LABORATORY   (United States)

Author keywords

Memory; NAND; Retention; TANOS

Indexed keywords

SILICON NITRIDE; TANTALUM COMPOUNDS;

CHARGE LOSS; CHARGE STORAGES; CHARGE TRAPS; FLASH MEMORY TRANSISTORS; FLOATING GATES; INITIAL STATE; MEMORY; MEMORY WINDOWS; MULTI LEVEL CELLS; NAND; PROCESS OPTIMIZATIONS; RETENTION; RETENTION CHARACTERISTICS; RETENTION IMPROVEMENTS; SUPPLY VOLTAGES; TANOS; TRAP LAYERS;

FLASH MEMORY;

EID: 62549154474     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2012397     Document Type: Article

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