Electron trap generation in high-k gate stacks by constant voltage stress

IEEE Transactions on Device and Materials Reliability

Volumn 6, Issue 2, 2006, Pages 123-131

  Young, Chadwin D ^a,b   Heh, Dawei ^a,b   Nadkarni, Suvid V ^c   Choi, Rino ^a,b   Peterson, Jeff J ^a,b   Barnett, Joel ^b   Lee, Byoung Hun ^a,b,d   Bersuker, Gennadi ^a,b  

^a IEEE   (United States)

^b SEMATECH   (United States)

^c UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^d IBM   (United States)

Author keywords

Charge pumping (CP); Charge trapping; High k; Threshold voltage instability; Trap generation

Indexed keywords

CHARGE PUMPING (CP); CHARGE TRAPPING; THRESHOLD VOLTAGE INSTABILITY; TRAP GENERATION; VOLTAGE STRESS;

ANNEALING; DEFECTS; ELECTRON TRAPS; SILICON COMPOUNDS; SURFACE CHEMISTRY; THICKNESS MEASUREMENT; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

DIELECTRIC MATERIALS;

EID: 33748108365     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2006.877865     Document Type: Conference Paper

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