Layered tunnel barriers for nonvolatile memory devices

Applied Physics Letters

Volumn 73, Issue 15, 1998, Pages 2137-2139

  Likharev, Konstantin K ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0000090297     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.122402     Document Type: Article

References (23)

1. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. (Wiley, New York, 1981).
2. B. Prince, Semiconductor Memories, 2nd ed. (Wiley, Chichester, UK, 1991);
3. in Nonvolatile Semiconductor Memory Technology, edited by W. D. Brown and J. E. Brewer (IEEE, New York, 1998).
4. C. L. Allyn, A. C. Gossard, and W. Weigmann, Appl. Phys. Lett. 36, 373 (1980).
5. R. J. Malik, T. R. AuCoin, R. L. Ross, K. Board, C. E. C. Wood, and L. F. Eastman, Electron. Lett. 16, 837 (1980).
6. F. Capasso, F. Beltram, R. J. Malik, and J. F. Walker, IEEE Electron Device Lett. 9, 377 (1988).
7. A somewhat similar effect may be achieved using grain-enriched interfaces [D. J. DiMaria and D. W. Dong, J. Appl. Phys. 51, 2722 (1980)]
8. electrode surface texturing [H. J. Buhlmann, M. Olcer, and M. Ilegems, Electron. Lett. 22, 212 (1986)]
9. or granular floating gates [H. I. Hanafi, S. Tiwari, and I. Khan, IEEE Trans. Electron Devices 43, 1553 (1996)], due to the electric field concentration on convex parts of the conductor surfaces. All these methods, however, are inherently irreproducible due to the randomness of the exact shape of the surfaces.
10. Silicon Nitride and Silicon Dioxide Thin Insulating Films, edited by V. J. Kapoor and K. T. Hankins (The Electrochemical Society, Pennington, NJ, 1987), pp. 7, 23;
11. V. I. Belyi, L. L. Vasilyeva, A. S. Ginovker, V. A. Gritsenko, S. M. Repinsky, S. P. Sinitsa, T. P. Smirnova, and F. L. Edelman, Silicon Nitride in Electronics (Elsevier, Amsterdam, 1987), pp. 148, 162;
12. S. Strite and H. Morkoç, J. Vac. Sci. Technol. B 10, 1237 (1992).
13. J. T. Wallmark and J. H. Scott, RCA Rev. 30, 335 (1969);
14. V. W. L. Chin, T. L. Lancey, and T. Osotchan, J. Appl. Phys. 75, 7365 (1994);
15. V. M. Bermudez et al. 79, 110 (1996).
16. 4 layers in less than a ns after the write/erase operation has been completed, making the cell ready for a new cycle.
17. L. Guo, E. Leobandung, and S. Chou, Appl. Phys. Lett. 70, 850 (1997);
18. F. G. Pikus and K. K. Likharev, 71, 3661 (1997).
19. A. N. Korotkov and K. K. Likharev, in: Proceedings of the 1995 ISDRS (University of Virginia Press, Charlottesville, VA, 1995), p. 355.
20. K. K. Likharev and A. N. Korotkov, VLSI Design (Amsterdam) 3, 341 (1997).
21. C. D. Chen, Y. Nakamura, and J. S. Tsai, Appl. Phys. Lett. 71, 2038 (1997).
22. M. J. Yoo, T. A. Fulton, H. F. Hess, R. L. Willett, L. N. Dunklebrger, R. J. Chichester, L. N. Pfeiffer, and K. W. West, Science 276, 579 (1997).
23. R. C. Barrett and C. F. Quate, J. Appl. Phys. 70, 2725 (1991).