Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

ACM Transactions on Design Automation of Electronic Systems

Volumn 15, Issue 4, 2010, Pages

  Shin, Youngsoo ^a   Seomun, Jun ^a   Choi, Kyu Myung ^b   Sakurai, Takayasu ^c  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Design methodology; Leakage current; Low power; Power gating; Standard cell; VLSI

Indexed keywords

DESIGN METHODOLOGY; LOW POWER; POWER GATINGS; STANDARD-CELL; VLSI;

DESIGN; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; MANAGEMENT; POWER GENERATION; STANDARDS;

VLSI CIRCUITS;

EID: 77958043152     PISSN: 10844309     EISSN: 15577309     Source Type: Journal    
DOI: 10.1145/1835420.1835421     Document Type: Article

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