메뉴 건너뛰기




Volumn , Issue , 2006, Pages 633-637

Power gating with multiple sleep modes

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRACES; ITS APPLICATIONS; LEAKAGE SAVINGS; MULTIPLE MODES; POWER GATINGS; POWER PENALTY; SINGLE MODE; WAKE-UP LATENCY;

EID: 84886734078     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.102     Document Type: Conference Paper
Times cited : (122)

References (8)
  • 1
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • S. Borkar, "Design challenges of technology scaling," IEEE Micro, Vol. 19, No. 4, pp. 23-29, 1999.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 2
    • 0346148452 scopus 로고    scopus 로고
    • Design and CAD challenges in sub-90 nm CMOS technologies
    • Nov
    • K. Bernstein, C. T. Chuang, R. Joshi and R. Puri, "Design and CAD challenges in sub-90 nm CMOS technologies," ICCAD, pp 129-136, Nov. 2003.
    • (2003) ICCAD , pp. 129-136
    • Bernstein, K.1    Chuang, C.T.2    Joshi, R.3    Puri, R.4
  • 3
    • 0029359285 scopus 로고
    • 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
    • Aug
    • S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," JSSC, vol. SC-30, pp. 847-854, Aug. 1995.
    • (1995) JSSC , vol.SC-30 , pp. 847-854
    • Mutoh, S.1
  • 4
    • 0031639695 scopus 로고    scopus 로고
    • MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
    • June
    • J. Kao, S. Narendra, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," DAC, pp. 495-500, June 1998.
    • (1998) DAC , pp. 495-500
    • Kao, J.1    Narendra, S.2    Chandrakasan, A.3
  • 5
    • 0034293891 scopus 로고    scopus 로고
    • A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current
    • Oct
    • H. Kawaguchi, K. Nose, and T. Sakura, "A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current," JSSC, vol. SC-35, pp. 1498-1501, Oct. 2000.
    • (2000) JSSC , vol.SC-35 , pp. 1498-1501
    • Kawaguchi, H.1    Nose, K.2    Sakura, T.3
  • 6
    • 0034863403 scopus 로고    scopus 로고
    • Enhanced multi-threshold (MTCMOS) circuits using variable well bias
    • Aug
    • S. Kosonocky, M. Immediato, P. Cottrell, T. Hook, R. Mann, and J. Brown, "Enhanced multi-threshold (MTCMOS) circuits using variable well bias," ISLPED, pp. 165-169, Aug. 2001.
    • (2001) ISLPED , pp. 165-169
    • Kosonocky, S.1    Immediato, M.2    Cottrell, P.3    Hook, T.4    Mann, R.5    Brown, J.6
  • 7
    • 0036049095 scopus 로고    scopus 로고
    • Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
    • June
    • M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," DAC, pp. 480-485, June 2002.
    • (2002) DAC , pp. 480-485
    • Anis, M.1    Areibi, S.2    Mahmoud, M.3    Elmasry, M.4
  • 8
    • 16244390217 scopus 로고    scopus 로고
    • Experimental measurement of a novel power gating structure with intermediate power saving mode
    • August
    • S. Kim, S. Kosonocky, D. Knebel, and K. Stawiasz, "Experimental measurement of a novel power gating structure with intermediate power saving mode", ISLPED, pp. 20-25, August 2004.
    • (2004) ISLPED , pp. 20-25
    • Kim, S.1    Kosonocky, S.2    Knebel, D.3    Stawiasz, K.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.