Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 7, 2006, Pages 1654-1660

  Henzler, Stephan ^a,b,c   Georgakos, Georg ^c   Eireiner, Matthias ^a,b   Nirschl, Thomas ^c   Pacha, Christian ^a,c   Berthold, Joerg ^c   Schmitt Landsiedel, Doris ^a,b  

^a IEEE   (Germany)

^b TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^c INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Leakage reduction; Low power; MTCMOS; Power gating; Retention flip flop; Sleep transistor; State retention

Indexed keywords

LEAKAGE REDUCTION; LOW POWER; MTCMOS; POWER GATING; RETENTION FLIP-FLOP; SLEEP TRANSISTOR; STATE RETENTION;

AMPLIFIERS (ELECTRONIC); ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; NETWORKS (CIRCUITS); POWER SUPPLY CIRCUITS; SIGNAL PROCESSING;

FLIP FLOP CIRCUITS;

EID: 33746346738     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.873218     Document Type: Conference Paper

References (8)

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