Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 6, 2007, Pages 512-516

  Kim, Hyung Ock ^a   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

Leakage; low power; power gating; semicustom; standard cell

Indexed keywords

CIRCUIT THEORY; CMOS INTEGRATED CIRCUITS; DECODING; DESIGN; LEAKAGE CURRENTS; VITERBI ALGORITHM;

POWER GATED CIRCUITS; SEMICUSTOM DESIGN METHODOLOGY;

LOGIC CIRCUITS;

EID: 34347376135     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.894414     Document Type: Article

References (14)

1. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, “A 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995.
2. K. Usami, N. Kawabe, M. Koizumi, K. Seta, and T. Furusawa, “Automated selective multi-threshold design for ultra-low standby applications,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2002, pp. 202–206.
3. T. Kitahara, N. Kawabe, F. Minami, K. Seta, and T. Furusawa, “Area-efficient selective multi-threshold CMOS design methodology for standby leakage power reduction,” in Proc. Design, Automat. and Test in Europe Conf. Exhib., Mar. 2005, pp. 646–647.
4. V. Zyuban and S. V. Kosonocky, “Low power integrated scan-retention mechanism,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2002, pp. 98–102
5. H.-S. Won, K.-S. Kim, K.-O. Jeong, K.-T. Park, K.-M. Choi, and J.-T. Kong, “An MTCMOS design methodology and its application to mobile computing,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2003, pp. 110–115.
6. S. Mutoh, S. Shigematsu, Y. Gotoh, and S. Konaka, “Design method of MTCMOS power switch for low-voltage high-speed LSIs,” in Proc. Asia South Pacific Design Automat. Conf., Jan. 1999, pp. 113–116.
7. S. Henzler et al., “Sleep transistor circuits for fine-grained power switch-off with short power-down times,” in Proc. IEEE Int. Solid-State Circuits Conf, Feb. 2005, pp. 302–303.
8. S. V. Kosonocky, M. Immediato, P. Cottrell, and T. Hook, “Enhanced multi-threshold (MTCMOS) circuits using variable well bias,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2001, pp. 165–169.
9. P. Babighian, L. Benini, A. Macii, and E. Macii, “Post-layout leakage power minimization based on distributed sleep transistor insertion,” in Proc. Int. Symp. Low Power Electron. Design, Aug. 2004, pp. 138–143.
10. P. Royannez et al., “90-nm low leakage SoC design techniques for wireless applications,” in Proc. IEEE Int. Solid-State Circuits Conf, Feb. 2006, pp. 138–139.
11. J. N. Kozhaya and L. A. Bakir, “An electrically robust method for placing power gating switches in voltage islands,” in Proc. Custom Integr. Circuits Conf, Oct. 2004, pp. 321–324.
12. J. Kao and A. Chandrakasan, “MTCMOS sequential circuits,” in Proc. Eur. Solid-State Circuits Conf, Sep. 2001, pp. 317–320.
13. S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada, “A 1-V high-speed MTCMOS circuit scheme for power-down application circuits,” IEEE J. Solid-State Circuits, vol. 32, no. 6, pp. 861–869, Jun. 1997.
14. M. Ketkar and S. S. Sapatnekar, “Standby power optimization via transistor sizing and dual threshold voltage assignment,” in Proc. Int. Conf. on Computer Aided Design, Nov. 2002, pp. 375–378.