An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 779-782

  Chen, Yu Ting ^a   Juan, Da Cheng ^a   Lee, Ming Chao ^a   Chang, Shih Chieh ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISSIPATION; TRANSISTORS; WAKES;

ACCURATE ESTIMATION; COMPUTER-AIDED DESIGN; DISTRIBUTED SLEEP TRANSISTOR NETWORK; ENERGY LOSSES; INTERNATIONAL CONFERENCES; POWER MODES; POWER-GATING; SURGE-CURRENT; UP TIME;

DESIGN;

EID: 50249124041     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397360     Document Type: Conference Paper

References (6)

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2. D. S. Chiou, S. H. Chen, S. C. Chang, and C. Yeh, "Timing Driven Power Gating," Proc. of the DAC, pp. 121-124, 2006.
3. S. Kim, S. V. Kosonocky, and D. R. Knebel, "Understanding and Minimizing Ground Bounce During Mode Transition of Power Gating Structures," Proc. of the ISLPED , Aug, 2003.
4. C. Long, and L. He, "Distributed Sleep Transistor Network for Power Reduction," IEEE Transaction on VLSI systems, vol. 12, no. 9, Sep. 2004.
5. A. Sagahyroon, and F. Aloul, "Maximum Power-Up Current Estimation in Combinational CMOS Circuits," Proc. of the IEEE MELECON, May 16-19, 2006.
6. K. Shi, and D. Howard, "Challenges in Sleep Transistor Design and Implementation in Low-Power Designs," Proc. of the DAC, pp. 113-116, 2006.