Low standby power state storage for sub-130-nm technologies

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 2, 2005, Pages 498-506

  Clark, Lawrence T ^a   Ricci, Franco ^b   Biyani, Manish ^b  

^a Arizona State University   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Leakage currents; Logic circuits; Low power; Sequential logic circuits

Indexed keywords

ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; FABRICATION; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; PERSONAL DIGITAL ASSISTANTS; TRANSISTORS;

CIRCUIT DESIGN; GATE INDUCED DRAIN LEAKAGE (GIDL); LOW POWER; SEQUENTIAL LOGIC CIRCUITS;

STANDBY POWER SYSTEMS;

EID: 13444270768     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.840987     Document Type: Article

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