Timing-driven row-based power gating

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 104-109

  Sathanur, Ashoka ^a   Pullini, Antonio ^a   Benini, Luca ^b   MacIi, Alberto ^a   MacIi, Enrico ^a   Poncino, Massimo ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Clustering; Leakage power; Power gating; Row based; Sleep transistor; Standard cell

Indexed keywords

LEAKAGE REDUCTION; POWER GATING; SLEEP TRANSISTORS; STANDARD CELLS;

BENCHMARKING; CLUSTERING ALGORITHMS; FORMAL LOGIC; LEAKAGE CURRENTS;

GATES (TRANSISTOR);

EID: 37049012269     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283803     Document Type: Conference Paper

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