Power-gating-aware high-level synthesis

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2008, Pages 39-44

  Choi, Eunjoo ^a   Shin, Changsik ^b   Kim, Taewhan ^c   Shin, Youngsoo ^a  

^a LG Electronics Inc   (South Korea)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Seoul National University   (South Korea)

Author keywords

High level synthesis; Leakage; Power gating

Indexed keywords

BENCHMARKING; CMOS INTEGRATED CIRCUITS; DESIGN; LOW POWER ELECTRONICS; SCHEDULING;

BENCHMARK DESIGNS; CIRCUIT LAYOUTS; CIRCUIT STATE; CMOS TECHNOLOGIES; CONTROLLER SYNTHESIS; DESIGN FRAMEWORKS; HIGH-LEVEL SYNTHESIS; INFLUENTIAL FACTORS; LATENCY CONSTRAINTS; LEAKAGE; POWER SAVINGS; POWER-GATING; SCHEDULING OPERATIONS; SCHEDULING PROBLEMS; STANDBY MODES; STATE RETENTIONS; WIRE LENGTHS;

POWER ELECTRONICS;

EID: 57549101899     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1393921.1393936     Document Type: Conference Paper

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