Challenges in sleep transistor design and implementation in low-power designs

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 113-116

  Shi, Kaijian ^a   Howard, David ^b  

^a SYNOPSYS INC   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

Low power design; Methodology; Power gating; Sleep transistor

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRIC CURRENT CONTROL; ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; GATES (TRANSISTOR); OPTIMIZATION;

LOW-POWER DESIGN; OPTIMUM POWER; POWER GATING; SLEEP TRANSISTOR;

TRANSISTORS;

EID: 34547218625     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146943     Document Type: Conference Paper

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