-
1
-
-
2442640116
-
Cellular phones as embedded systems
-
Y. Neuvo, "Cellular phones as embedded systems," in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 32-37.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
, pp. 32-37
-
-
Neuvo, Y.1
-
2
-
-
84863858551
-
A fully integrated SoC for GSM/GPRS in 0.13 μm CMOS
-
J. Kissing et al., "A fully integrated SoC for GSM/GPRS in 0.13 μm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 1942-1951.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 1942-1951
-
-
Kissing, J.1
-
3
-
-
28144444694
-
90nmlow leakage SoC design techniques for wireless applications
-
P. Royannez et al., "90nmlow leakage SoC design techniques for wireless applications," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 138, 589.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
-
-
Royannez, P.1
-
4
-
-
2442702703
-
A resume-standby application processor for 3G cellular phones
-
T. Kamei et al., "A resume-standby application processor for 3G cellular phones "in IEEE ISSCC Dig. Tech. Papers, 2004, pp. 336, 531.
-
(2004)
IEEE ISSCC Dig. Tech. Papers
-
-
Kamei, T.1
-
5
-
-
28144450093
-
A reprogrammable EDGE baseband and multimedia handset SoC with 6 Mb embedded DRAM
-
A. Cofler, F. Druilhe, D. Dutoit, and M. Harrand, "A reprogrammable EDGE baseband and multimedia handset SoC with 6 Mb embedded DRAM," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 448, 609.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
-
-
Cofler, A.1
Druilhe, F.2
Dutoit, D.3
Harrand, M.4
-
6
-
-
0036049224
-
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
-
T. Schafbauer et al., "Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology," in Symp. VLSI Technology Dig. Papers, 2002, pp. 62-63.
-
(2002)
Symp. VLSI Technology Dig. Papers
, pp. 62-63
-
-
Schafbauer, T.1
-
7
-
-
0037686711
-
Low-power circuits and technology for wireless digital systems
-
Mar
-
S. V. Kosonocky et al., "Low-power circuits and technology for wireless digital systems," IBM J. Res. Devel., vol. 47, no. 23, pp. 283-298, Mar. 2003.
-
(2003)
IBM J. Res. Devel
, vol.47
, Issue.23
, pp. 283-298
-
-
Kosonocky, S.V.1
-
8
-
-
0034230287
-
Dual-threshold voltage techniques for low-power digital circuits
-
Jul
-
J. T. Kao et al., "Dual-threshold voltage techniques for low-power digital circuits," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1009-1018, Jul. 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, Issue.7
, pp. 1009-1018
-
-
Kao, J.T.1
-
9
-
-
0036858657
-
A 32-bit power PC system-on-a chip with support for dynamic voltage scaling and dynamic frequency scaling
-
Nov
-
K. J. Nowka et al., "A 32-bit power PC system-on-a chip with support for dynamic voltage scaling and dynamic frequency scaling," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1441-1447, Nov. 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.11
, pp. 1441-1447
-
-
Nowka, K.J.1
-
10
-
-
13444270768
-
Low standby power state storage for sub-130-nmtechnologies
-
Feb
-
L. T. Clark, F. Rici, and M. Biyani, "Low standby power state storage for sub-130-nmtechnologies," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 498-506, Feb. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.2
, pp. 498-506
-
-
Clark, L.T.1
Rici, F.2
Biyani, M.3
-
11
-
-
0036958067
-
Low power integrated scan-retention mechanism
-
V. Zyuban and S. Kosonocky, "Low power integrated scan-retention mechanism," in Proc. ISLPED, 2002, pp. 98-102.
-
(2002)
Proc. ISLPED
, pp. 98-102
-
-
Zyuban, V.1
Kosonocky, S.2
-
12
-
-
28144454988
-
Sleep transistor circuits for fine-grained power switch-off with short power-down times
-
S. Henzler et al., "Sleep transistor circuits for fine-grained power switch-off with short power-down times," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 302, 600.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
-
-
Henzler, S.1
-
13
-
-
28144434543
-
A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies
-
K. von Arnim et al., "A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 380, 605.
-
(2005)
IEEE ISSCC Dig. Tech. Papers
-
-
von Arnim, K.1
-
14
-
-
0036474788
-
A 1.2 GIPS /W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias
-
Feb
-
M. Miyazaki et al., "A 1.2 GIPS /W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias," IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 201-217, Feb. 2002, 2005.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, Issue.2
, pp. 201-217
-
-
Miyazaki, M.1
-
15
-
-
22544440903
-
Efficiency of body biasing in 90 nm CMOS for low power digital circuits
-
Jul
-
K. von Arnim et al., "Efficiency of body biasing in 90 nm CMOS for low power digital circuits," IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1549-1553, Jul. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.7
, pp. 1549-1553
-
-
von Arnim, K.1
-
16
-
-
33845197614
-
A 256kb sub-threshold SRAM in 65nm CMOS
-
B. Calhoun et al., "A 256kb sub-threshold SRAM in 65nm CMOS," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 2592-2601.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 2592-2601
-
-
Calhoun, B.1
-
18
-
-
33846203102
-
-
T. Luftner, J. Berthold, C. Pacha, G. Georgakos, G Sauzon, O. Homke, J. Beshenar, P. Mahrla, K. Just, and P. HoberS. Henzler, D. Schmitt-Landsieder, A. Yakovleff, A. Klein, R. Knight, P. Acharya, H. Mabrouki, G. Juhoor, and M. Sauer, Sense amplifier-based flip-flop, in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 952-961.
-
T. Luftner, J. Berthold, C. Pacha, G. Georgakos, G Sauzon, O. Homke, J. Beshenar, P. Mahrla, K. Just, and P. HoberS. Henzler, D. Schmitt-Landsieder, A. Yakovleff, A. Klein, R. Knight, P. Acharya, H. Mabrouki, G. Juhoor, and M. Sauer, "Sense amplifier-based flip-flop," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 952-961.
-
-
-
|